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參數(shù)資料
| 型號： | ADF4113HVBRUZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | High Voltage Charge Pump, PLL Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3700 MHz, PDSO16 |
| 封裝： | LEAD FREE, MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 385K |
| 代理商： | ADF4113HVBRUZ-RL7 |
ADF4113HV
SPECIFICATIONS
AV
DD
= DV
DD
= 3 V ± 10%, 5 V ± 10%; 13.5 V < V
P
≤ 16.5 V; AGND = DGND = CPGND = 0 V; R
SET
= 4.7 kΩ; dBm referred to 50 Ω;
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Operating temperature range for B version: 40°C to +85°C.
Table 1.
Parameter
B Version
B Chips
1
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
15/0
15/0
RF Input Frequency
0.2/3.7
0.2/3.7
Prescaler Output Frequency
2
165
165
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
10/0
10/0
RF Input Frequency
0.2/3.7
0.2/3.7
0.2/4.0
0.2/4.0
Prescaler Output Frequency
200
200
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
5/150
5/150
Reference Input Sensitivity
0.4/AV
DD
0.4/AV
DD
1.0/AV
DD
1.0/AV
DD
REF
IN
Input Capacitance
10
10
REF
IN
Input Current
±100
±100
PHASE DETECTOR FREQUENCY
5
5
CHARGE PUMP
I
CP
Sink/Source
High Value
640
640
Low Value
80
80
Absolute Accuracy
2.5
2.5
R
SET
Range
3.9/10
3.9/10
I
CP
Three-State Leakage Current
5
5
Sink and Source Current Matching
3
3
I
CP
vs. V
CP
1.5
1.5
I
CP
vs. Temperature
2
2
LOGIC INPUTS
V
INH
, Input High Voltage
0.8 × DV
DD
0.8 × DV
DD
V
INL
, Input Low Voltage
0.2 × DV
DD
0.2 × DV
DD
I
INH
/I
INL
, Input Current
±1
±1
C
IN
, Input Capacitance
10
10
LOGIC OUTPUTS
V
OH
, Output High Voltage
DV
DD
0.4
DV
DD
0.4
V
OL
, Output Low Voltage
0.4
0.4
POWER SUPPLIES
AV
DD
2.7/5.5
2.7/5.5
DV
DD
AV
DD
AV
DD
V
P
13.5/16.5
13.5/16.5
I
DD5
(AI
DD
DD
+ DI )
16
11
I
P
0.25
0.25
Low Power Sleep Mode
1
1
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
6
212
212
1
The B chip specifications are given as typical values.
2
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3
AC coupling ensures AV
DD
/2 bias.
4
Guaranteed by characterization.
5
T
A
= 25
o
C; AV
DD
= DV
DD
= 5.5 V; P = 16; RF
IN
= 900 MHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN
TOT
, and subtracting 20logN (where N is the N divider
value) and 10logf
PFD
: PN
SYNTH
= PN
TOT
10logf
PFD
20logN.
Rev. 0 | Page 3 of 20
Unit
dBm min/max
GHz min/max
MHz max
dBm min/max
GHz min/max
GHz min/max
MHz max
MHz min/max
V p-p min/max
V p-p min/max
pF max
μA max
MHz max
μA typ
μA typ
% typ
kΩ typ
nA max
% typ
% typ
% typ
V min
V max
μA max
pF max
V min
V max
V min/V max
V min/V max
mA max
mA max
μA typ
dBc/Hz typ
Test Conditions/Comments
For lower frequencies, ensure SR > 130 V/μs
For lower frequencies, ensure SR > 130 V/μs
Input level = 5 dBm
For f < 5 MHz, ensure SR > 100 V/μs
AV
DD
= 3.3 V, biased at AV
DD
/2
3
For f ≥ 10 MHz, AV
DD
= 5 V, biased at AV
DD
/2
3, 4
R
SET
= 4.7 kΩ
1 V ≤ V
CP
≤ V
P
– 1 V
1 V ≤ V
CP
≤ V
P
– 1 V
V
CP
= V
P
/2
I
OH
= 500 μA
I
OL
= 500 μA
11 mA typical
T
A
= 25°C
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