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參數(shù)資料
| 型號(hào)： | ADF4110BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類(lèi)型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 550MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF411XEBZ1-ND - BOARD EVAL FOR ADF411X NO CHIP |
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Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 21 of 28
RESYNCHRONIZING THE PRESCALER OUTPUT
Table 7 (the Reference Counter Latch Map) shows two bits,
DB22 and DB21, which are labeled DLY and SYNC,
respectively. These bits affect the operation of the prescaler.
With SYNC = 1, the prescaler output is resynchronized with the
RF input. This has the effect of reducing jitter due to the
prescaler and can lead to an overall improvement in synthesizer
phase noise performance. Typically, a 1 dB to 2 dB
improvement is seen in the ADF4113. The lower bandwidth
devices can show an even greater improvement. For example,
the ADF4110 phase noise is typically improved by 3 dB when
SYNC is enabled.
With DLY = 1, the prescaler output is resynchronized with a
delayed version of the RF input.
If the SYNC feature is used on the synthesizer, some care must
be taken. At some point, (at certain temperatures and output
frequencies), the delay through the prescaler coincides with the
active edge on RF input; this causes the SYNC feature to break
down. It is important to be aware of this when using the SYNC
feature. Adding a delay to the RF signal, by programming
DLY = 1, extends the operating frequency and temperature
somewhat. Using the SYNC feature also increases the value of
the AIDD for the device. With a 900 MHz output, the ADF4113
AIDD increases by about 1.3 mA when SYNC is enabled and by
an additional 0.3 mA if DLY is enabled.
All the typical performance plots in this data sheet, except for
Figure 8, apply for DLY and SYNC = 0, i.e., no resynchroniza-
tion or delay enabled.
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| ADF4111BCPZ | 功能描述:IC PLL RF FREQ SYNTHESZR 20LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):NJW1504V-TE1-NDNJW1504V-TE1TR |
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