參數(shù)資料
型號： ADF4108BRUZ-RL7
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： PLL Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 8000 MHz, PDSO16
封裝： LEAD FREE, TSSOP-16
文件頁數(shù)： 3/20頁
文件大?。?/td> 350K
代理商： ADF4108BRUZ-RL7
ADF4108
SPECIFICATIONS
AV
DD
= DV
DD
= 3.3 V ± 2%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 1.
B Chips
2
(Typ)
Unit
RF CHARACTERISTICS
RF Input Frequency (RF
IN
)
1.0/8.0
1.0/8.0
GHz min/max
RF Input Sensitivity
5/+5
5/+5
dBm min/max
Maximum Allowable Prescaler
Output Frequency
3
325
325
MHz max
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
20/250
20/250
MHz min/max
REF
IN
Input Sensitivity
4
0.8/V
DD
0.8/V
DD
V p-p min/max
REF
IN
Input Capacitance
10
10
pF max
REF
IN
Input Current
±100
±100
μA max
PHASE DETECTOR
Phase Detector Frequency
6
104
104
MHz max
CHARGE PUMP
I
CP
Sink/Source
High Value
5
5
mA typ
Low Value
625
625
μA typ
Absolute Accuracy
2.5
2.5
% typ
R
SET
Range
3.0/11
3.0/11
kΩ typ
I
CP
Three-State Leakage
1
1
nA typ
Sink and Source Current
Matching
I
CP
vs. V
CP
1.5
1.5
% typ
I
CP
vs. Temperature
2
2
% typ
LOGIC INPUTS
V
IH
, Input High Voltage
1.4
1.4
V min
V
IL
, Input Low Voltage
0.6
0.6
V max
I
INH
, I
INL
, Input Current
±1
±1
μA max
C
IN
, Input Capacitance
10
10
pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage
1.4
1.4
V min
V
OH
, Output High Voltage
V
DD
0.4
V
DD
0.4
V min
I
OH
100
100
μA max
V
OL
, Output Low Voltage
0.4
0.4
V max
POWER SUPPLIES
AV
DD
3.2/3.6
3.2/3.6
V min/V max
DV
DD
AV
DD
AV
DD
V
P
AV
DD
/5.5
AV
DD
/5.5
V min/V max
I
DD
(AI
DD
+ DI
DD
)
7
17
17
mA max
I
P
0.4
0.4
mA max
Power-Down Mode (AI
DD
+ DI
DD
)
8
10
10
μA typ
Rev. 0 | Page 3 of 20
Parameter
B Version
1
Test Conditions/Comments
See Figure 12 for input circuit
For lower frequencies ensure slew rate (SR) > 320 V/μs
P = 8
P = 16
For f < 20 MHz, ensure SR > 50 V/μs
Biased at AV
DD
/2
5
Programmable; see Figure 19
With R
SET
= 5.1 kΩ
With R
SET
= 5.1 kΩ
See Figure 19
1 nA typical; T
A
= 25°C
0.5 V ≤ V
CP
≤ V
P
– 0.5 V
300
300
MHz max
2
2
% typ
0.5 V ≤ V
CP
≤ V
P
– 0.5 V
V
CP
= V
P
/2
Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V
CMOS output chosen
I
OL
= 500 μA
AV
DD
≤ V
P
≤ 5.5 V
15 mA typ
T
A
= 25°C
相關(guān)PDF資料
PDF描述
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