
PLL Frequency Synthesizer
ADF4108
FEATURES
8.0 GHz bandwidth
3.2 V to 3.6 V power supply
Separate charge pump supply (V
P
) allows extended tuning
voltage in 3.3 V systems
Programmable, dual modulus prescaler 8/9, 16/17, 32/33, or
64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Loop filter design possible with ADIsimPLL
Rev. 0
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2006 Analog Devices, Inc. All rights reserved.
www.analog.com
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
GENERAL DESCRIPTION
The ADF4108 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise digital PFD (phase frequency detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual-
modulus prescaler (P/P + 1), implement an N divider (N =
BP + A). In addition, the 14-bit reference counter (R counter),
allows selectable REFIN frequencies at the PFD input. A
complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
FUNCTIONAL BLOCK DIAGRAM
CLK
DATA
LE
REF
IN
RF
IN
A
RF
IN
B
24-BIT INPUT
REGISTER
SD
OUT
AV
DD
DV
DD
CE
AGND
DGND
14-BIT
R COUNTER
R COUNTER
LATCH
22
14
FUNCTION
LATCH
A, B COUNTER
LATCH
FROM
FUNCTION
LATCH
PRESCALER
P/P + 1
N = BP + A
LOAD
LOAD
13-BIT
B COUNTER
6-BIT
A COUNTER
6
19
13
M3 M2 M1
MUX
SD
OUT
AV
DD
HIGH Z
MUXOUT
CPGND
R
SET
V
P
CP
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
REFERENCE
CHARGE
PUMP
CURRENT
SETTING 1
ADF4108
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
CURRENT
SETTING 2
0
Figure 1.