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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ADF4106BRU
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 21/24闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC PLL FREQ SYNTHESIZER 16-TSSOP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 96
椤炲瀷锛� 鏅�(sh铆)閻�/闋荤巼鍚堟垚鍣紝RF
PLL锛� 鏄�
杓稿叆锛� CMOS锛孴TL
杓稿嚭锛� 鏅�(sh铆)閻�
闆昏矾鏁�(sh霉)锛� 1
姣旂巼 - 杓稿叆:杓稿嚭锛� 2:1
宸垎 - 杓稿叆:杓稿嚭锛� 鏄�/鐒�
闋荤巼 - 鏈€澶э細 6GHz
闄ゆ硶鍣�/涔樻硶鍣細 鐒�/鐒�
闆绘簮闆诲锛� 2.7 V ~ 3.3 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 16-TSSOP锛�0.173"锛�4.40mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 16-TSSOP
鍖呰锛� 绠′欢
閰嶇敤锛� EVAL-ADF4106EBZ1-ND - BOARD EVAL FOR ADF4106
ADF4106
Data Sheet
Rev. E | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25掳C, unless otherwise noted.
Table 3.
Parameter
Rating
AVDD to GND1
鈥�0.3 V to + 3.6 V
AVDD to DVDD
鈥�0.3 V to + 0.3 V
VP to GND
鈥�0.3 V to + 5.8 V
VP to AVDD
鈥�0.3 V to + 5.8 V
Digital I/O Voltage to GND
鈥�0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND
鈥�0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND
鈥�0.3 V to VDD + 0.3 V
RFINA to RFINB
卤320 mV
Operating Temperature Range
Industrial (B Version)
鈥�40掳C to +85掳C
Storage Temperature Range
鈥�65掳C to +125掳C
Maximum Junction Temperature
150掳C
TSSOP 胃JA Thermal Impedance
112掳C/W
LFCSP 胃JA Thermal Impedance
(Paddle Soldered)
30.4掳C/W
Reflow Soldering
Peak Temperature
260掳C
Time at Peak Temperature
40 sec
Transistor Count
CMOS
6425
Bipolar
303
1
GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ADF4106BRU-REEL 鍔熻兘鎻忚堪:IC PLL FREQ SYNTHESIZER 16-TSSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅�(sh铆)閻�/瑷�(j矛)鏅�(sh铆) - 鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:Precision Edge® 椤炲瀷:鏅�(sh铆)閻�/闋荤巼鍚堟垚鍣� PLL:鐒� 杓稿叆:CML锛孭ECL 杓稿嚭:CML 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:2:1 宸垎 - 杓稿叆:杓稿嚭:鏄�/鏄� 闋荤巼 - 鏈€澶�:10.7GHz 闄ゆ硶鍣�/涔樻硶鍣�:鐒�/鐒� 闆绘簮闆诲:2.375 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:16-VFQFN 瑁搁湶鐒婄洡锛�16-MLF? 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-MLF?锛�3x3锛� 鍖呰:甯跺嵎 (TR) 鍏跺畠鍚嶇ū:SY58052UMGTRSY58052UMGTR-ND
ADF4106BRU-REEL7 鍔熻兘鎻忚堪:IC PLL FREQ SYNTHESIZER 16-TSSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅�(sh铆)閻�/瑷�(j矛)鏅�(sh铆) - 鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:Precision Edge® 椤炲瀷:鏅�(sh铆)閻�/闋荤巼鍚堟垚鍣� PLL:鐒� 杓稿叆:CML锛孭ECL 杓稿嚭:CML 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:2:1 宸垎 - 杓稿叆:杓稿嚭:鏄�/鏄� 闋荤巼 - 鏈€澶�:10.7GHz 闄ゆ硶鍣�/涔樻硶鍣�:鐒�/鐒� 闆绘簮闆诲:2.375 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:16-VFQFN 瑁搁湶鐒婄洡锛�16-MLF? 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-MLF?锛�3x3锛� 鍖呰:甯跺嵎 (TR) 鍏跺畠鍚嶇ū:SY58052UMGTRSY58052UMGTR-ND
ADF4106BRUZ 鍔熻兘鎻忚堪:IC PLL FREQ SYNTHESIZER 16-TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅�(sh铆)閻�/瑷�(j矛)鏅�(sh铆) - 鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,000 绯诲垪:- 椤炲瀷:PLL 闋荤巼鍚堟垚鍣� PLL:鏄� 杓稿叆:鏅堕珨 杓稿嚭:鏅�(sh铆)閻� 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:1:1 宸垎 - 杓稿叆:杓稿嚭:鐒�/鐒� 闋荤巼 - 鏈€澶�:1GHz 闄ゆ硶鍣�/涔樻硶鍣�:鏄�/鐒� 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:-20°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:16-LSSOP锛�0.175"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-SSOP 鍖呰:甯跺嵎 (TR) 鍏跺畠鍚嶇ū:NJW1504V-TE1-NDNJW1504V-TE1TR
ADF4106BRUZ 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:PLL/FREQUENCY SYNTHESIZER IC
ADF4106BRUZ-R7 鍔熻兘鎻忚堪:IC PLL FREQ SYNTHESIZER 16TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏅�(sh铆)閻�/瑷�(j矛)鏅�(sh铆) - 鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:Precision Edge® 椤炲瀷:鏅�(sh铆)閻�/闋荤巼鍚堟垚鍣� PLL:鐒� 杓稿叆:CML锛孭ECL 杓稿嚭:CML 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:2:1 宸垎 - 杓稿叆:杓稿嚭:鏄�/鏄� 闋荤巼 - 鏈€澶�:10.7GHz 闄ゆ硶鍣�/涔樻硶鍣�:鐒�/鐒� 闆绘簮闆诲:2.375 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:16-VFQFN 瑁搁湶鐒婄洡锛�16-MLF? 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:16-MLF?锛�3x3锛� 鍖呰:甯跺嵎 (TR) 鍏跺畠鍚嶇ū:SY58052UMGTRSY58052UMGTR-ND
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*鍨嬭櫉 *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉 灏佽
娣诲姞鏇村閲囪臣

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