參數(shù)資料
型號(hào)： ADF4106BCP
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： PLL Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 6000 MHz, QCC20
封裝： 4 X 4 MM, MO-220VGGD-1, LFCSP-20
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 228K
代理商： ADF4106BCP
REV. 0
ADF4106
–18–
On first applying power to the ADF4106, it needs at three writes
(one each to the R counter latch, the N counter latch and the
function latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control
power-down (CE input) and to detect lock (MUXOUT config-
ured as lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be 166kHz.
ADuC812
ADF4106
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
I/O PORTS
Figure 8. ADuC812 to ADF4106 Interface
ADSP-2181 Interface
Figure 9 shows the interface between the ADF4106 and the
ADSP-21xx Digital Signal Processor. The ADF4106 needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate Framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated. Set up the word length for
8 bits and use three memory locations for each 24-bit word. To
program each 24-bit latch, store the three 8-bit bytes, enable the
Autobuffered mode and then write to the transmit register of the
DSP. This last operation initiates the autobuffer transfer.
ADSP-21xx
ADF4106
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
I/O FLAGS
TFS
Figure 9. ADSP-21xx to ADF4106 Interface
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ADF4106BCPZ 制造商:Analog Devices 功能描述:IC FREQ SYNTHESIZER
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