參數(shù)資料
型號(hào)： ADF4002BRUZ
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： Phase Detector/Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 400 MHz, PDSO16
封裝： ROHS COMPLIANT, MO-153AB, TSSOP-16
文件頁數(shù)： 3/24頁
文件大?。?/td> 336K
代理商： ADF4002BRUZ
ADF4002
SPECIFICATIONS
AV
DD
= DV
DD
= 3 V ± 10%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω,
T
A
= T
MAX
to T
MIN
, unless otherwise noted.
Table 1.
B Version
1
Parameter
Min
Typ
RF CHARACTERISTICS
RF Input Sensitivity
10
RF Input Frequency (RF
IN
)
5
REFIN CHARACTERISTICS
REFIN Input Frequency
20
REFIN Input Sensitivity
2
0.8
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
4
CHARGE PUMP
I
CP
Sink/Source
High Value
5
Low Value
625
Absolute Accuracy
2.5
R
SET
Range
3.0
I
CP
Three-State Leakage
1
I
CP
vs. V
CP
1.5
Sink and Source Current Matching
2
I
CP
vs. Temperature
2
LOGIC INPUTS
V
IH
, Input High Voltage
1.4
V
IL
, Input Low Voltage
I
INH
, I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
1.4
V
OH
, Output High Voltage
V
DD
– 0.4
I
OH
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
2.7
DV
DD
AV
DD
V
P
AV
DD
I
DD5
(AI
DD
DD
+ DI )
5.0
I
P
Power-Down Mode
1
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
6
–222
1
Operating temperature range (B version) is –40°C to +85°C.
2
AV
DD
= DV
DD
= 3 V.
3
AC coupling ensures AV
DD
/2 bias.
4
Guaranteed by design. Sample tested to ensure compliance. Use of the PFD at frequencies above 104 MHz requires the minimum antibacklash pulse width enabled.
5
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; RF
IN
= 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN
frequency in MHz.
6
The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)
and 10logF
PFD
. PN
SYNTH
= PN
TOT
– 10logF
PFD
– 20logN. All phase noise measurements were performed with an Agilent E5500 phase noise test system, using the EVAL-
ADF4002EB1 and the HP8644B as the PLL reference.
Rev. 0 | Page 3 of 24
Unit
dBm
MHz
MHz
V p-p
pF
μA
MHz
mA
μA
%
kΩ
nA
%
%
%
V
V
μA
pF
V
V
μA
V
V
V
mA
mA
μA
dBc/Hz
Test Conditions/Comments
See Figure 12 for input circuit
For RF
IN
< 5 MHz, ensure slew rate (SR) > 4 V/μs
For REFIN < 20 MHz, ensure SR > 50 V/μs
Biased at AV
DD
/2
3
Programmable, see Figure 19
With R
SET
= 5.1 kΩ
With R
SET
= 5.1 kΩ
See Figure 19
T
A
= 25°C
0.5 V ≤ V
CP
≤ V
P
– 0.5 V
0.5 V ≤ V
CP
≤ V
P
– 0.5 V
V
CP
= V
P
/2
Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V
CMOS output chosen
I
OL
= 500 μA
AV
DD
≤ V
P
≤ 5.5 V
T
A
= 25°C
AI
DD
+ DI
DD
Max
0
400
300
V
DD
10
±100
200
11
0.6
±1
10
100
0.4
3.3
5.5
6.0
0.4
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