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參數(shù)資料
| 型號： | ADF4002BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 16-TSSOP |
| 設計資源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器（RF），相位檢測器 |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002 |
ADF4002
Data Sheet
Rev. C | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RSET
CP
CPGND
AGND
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RFINB
RFINA
AVDD
REFIN
VP
DVDD
ADF4002
TOP VIEW
(Not to Scale)
06052-
002
PIN 1
INDICATOR
Figure 3. TSSOP Pin Configuration (Top View)
15 MUXOUT
14 LE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
20
C
P
11 CE
6
7
8
DG
ND
9
DG
ND
10
4
5
19
18
17
16
RFINB
RFINA
R
SET
V
P
DV
DD
DV
DD
A
V
DD
A
V
DD
RE
F
IN
PIN 1
INDICATOR
ADF4002
TOP VIEW
(Not to Scale)
06052-
003
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
Figure 4. LFCSP Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAX
CP
R
I
25.5
=
where RSET = 5.1 k and ICPMAX = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter that, in turn, drives the
external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the RF input.
5
4
RFINB
Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 11.
6
5
RFINA
Input to the RF Input. This small signal input is ac-coupled to the external VCO.
7
6, 7
AVDD
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to the AVDD pin. AVDD must be the same value as DVDD.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100 k. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can
be ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking this pin high powers up the device, depending on the status of the Power-Down Bit F2.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches; the latch is selected using the control bits.
14
15
MUXOUT
Multiplexer Output. This allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
15
16, 17
DVDD
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16
18
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
EP
Exposed Pad. The exposed pad must be connected to AGND.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADF4002BRUZ-RL7 | 功能描述:IC PLL FREQUENCY SYNTH 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4002SRU-EP | 制造商:Analog Devices 功能描述:Phase Detector/Frequency Synthesizer 16-Pin TSSOP 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE - Rail/Tube 制造商:Analog Devices 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Low Frequency PLL Clock Source |
| ADF4002SRU-EP-RL7 | 制造商:Analog Devices 功能描述:Phase Detector/Frequency Synthesizer 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE - Tape and Reel 制造商:Analog Devices 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Low Frequency PLL Clock Source |
| ADF4002SRUZ-EP | 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:96 |
| ADF4002SRUZ-EP-RL7 | 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:1,000 |
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