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參數(shù)資料
| 型號： | ADF4002BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 20-LFCSP |
| 設計資源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) |
| 標準包裝： | 1,500 |
| 類型： | 時鐘/頻率合成器（RF），相位檢測器 |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002 |
Data Sheet
ADF4002
Rev. C | Page 17 of 20
APPLICATIONS
VERY LOW JITTER ENCODE CLOCK FOR HIGH
SPEED CONVERTERS
Figure 20 shows the ADF4002 with a VCXO to provide the
encode clock for a high speed analog-to-digital converter (ADC).
The converter used in this application is an AD9215-80, a 12-bit
converter that accepts up to an 80 MHz encode clock. To realize
a stable low jitter clock, use a 77.76 MHz, narrow band VCXO.
This example assumes a 19.44 MHz reference clock.
To minimize the phase noise contribution of the ADF4002, the
smallest multiplication factor of 4 is used. Thus, the R divider is
programmed to 1, and the N divider is programmed to 4.
The charge pump output of the ADF4002 (Pin 2) drives the
loop filter. The loop filter bandwidth is optimized for the best
possible rms jitter, a key factor in the signal-to-noise ratio
(SNR) of the ADC. Too narrow a bandwidth allows the VCXO
noise to dominate at small offsets from the carrier frequency.
Too wide a bandwidth allows the ADF4002 noise to dominate at
offsets where the VCXO noise is lower than the ADF4002 noise.
Thus, the intersection of the VCXO noise and the ADF4002 in-
band noise is chosen as the optimum loop filter bandwidth.
The design of the loop filter uses the ADIsimPLL (Version 3.0)
and is available as a free download from www.analog.com/pll.
The rms jitter is measured at <1.2 ps. This level is lower than
the maximum allowable 6 ps rms required to ensure the
theoretical SNR performance of 59 dB for this converter.
The setup shown in Figure 20 using the ADF4002, AD9215, and
HSC-ADC-EVALA-SC allows the user to quickly and effectively
determine the suitability of the converter and encode clock. The
SPI interface is used to control the ADF4002, and the USB inter-
face helps control the operation of the AD9215-80. The controller
board sends back FFT information to the PC that, if using an
ADC analyzer, provides all conversion results from the ADC.
VCXO: 77.76MHz
HC-ADC-EVALA-SC
PC
US
B
TCXO:
19.44MHz
ENCODE
CLOCK
AIN
ADF4002
N = 4
PD
R = 1
SPI
AGILENT:
500kHz, 1.8V p-p
06052-
034
AD9215-80
Figure 20. ADF4002 as Encode Clock
PFD
As the ADF4002 permits both R and N counters to be pro-
grammed to 1, the part can effectively be used as a standalone
PFD and charge pump. This is particularly useful in either a
clock cleaning application or a high performance LO. Addi-
tionally, the very low normalized phase noise floor (222 dBc/Hz)
enables very low in-band phase noise levels. It is possible to
operate the PFD up to a maximum frequency of 104 MHz.
In Figure 21, the reference frequency equals the PFD; therefore,
R = 1. The charge pump output integrates into a stable control
voltage for the VCXO, and the output from the VCXO is divided
down to the desired PFD frequency using an external divider.
06052-
035
8
2
16
15
7
6
5
9
4
3
1
REFIN
RSET
RFINA
RFINB
AV
DD
DV
DD
CP
G
ND
AG
ND
DG
ND
VDD
VP
V
P
CE
ADF4002
DECOUPLING CAPACITORS AND
INTERFACE SIGNALS HAVE BEEN
OMITTED FROM THE DIAGRAM IN
THE INTERESTS OF GREATER
CLARITY.
100pF
51
10k
LOOP
FILTER
GND
VCO
OR
VCXO
VCC
GND
EXTERNAL PRESCALER
18
18
18
100pF
RFOUT
VCC
Figure 21. ADF4002 as a PFD
INTERFACING
The ADF4002 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When the latch enable (Pin LE) goes high, the 24 bits
that have been clocked into the input register on each rising
edge of CLK are transferred to the appropriate latch. For more
information, see Figure 2 for the timing diagram and Table 6 for
the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
833 kHz, or one update every 1.2 s. This is certainly more than
adequate for systems that have typical lock times in hundreds of
microseconds.
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