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參數(shù)資料
| 型號： | ADF4002BCPZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Phase Detector/Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 400 MHz, QCC20 |
| 封裝： | ROHS COMPLIANT, MO-220VGGD-1, LFCSP-20 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 336K |
| 代理商： | ADF4002BCPZ-RL7 |
ADF4002
THEORY OF OPERATION
REFERENCE INPUT SECTION
Rev. 0 | Page 8 of 24
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
100k
NC
REF
IN
NC
NO
SW1
SW2
BUFFER
SW3
TO R COUNTER
POWER-DOWN
CONTROL
0
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the N counter.
500
1.6V
500
AGND
BIAS
GENERATOR
RF
IN
A
RF
IN
B
AV
DD
0
Figure 12. RF Input Stage
N COUNTER
The N CMOS counter allows a wide ranging division ratio in
the PLL feedback counter. Division ratios from 1 to 8191 are
allowed.
N and R Relationship
The N counter makes it possible to generate output frequencies
that are spaced only by the reference frequency divided by R.
The equation for the VCO frequency is
R
REFIN
f
N
VCO
f
×
=
where:
f
VCO
is the output frequency of external voltage controlled
oscillator (VCO).
N
is the preset divide ratio of binary 13-bit counter (1 to 8191).
f
REFIN
is the external reference frequency oscillator.
TO PFD
FROM RF
INPUT STAGE
FROM N
COUNTER LATCH
13-BIT N
COUNTER
0
Figure 13. N Counter
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function, and
minimizes phase noise and reference spurs. Two bits in the
reference counter latch (ABP2 and ABP1) control the width of
the pulse. See Figure 17 for details. The smallest antibacklash
pulse width (1.3 ns) should be used if the desired PFD exceeds
104 MHz.
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| ADF4002BRUZ | 功能描述:IC PLL FREQUENCY SYNTH 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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