參數(shù)資料
型號: ADF4002
廠商: Analog Devices, Inc.
英文描述: Phase Detector/Frequency Synthesizer
中文描述: 相位檢測器/頻率合成器
文件頁數(shù): 6/24頁
文件大?。?/td> 336K
代理商: ADF4002
ADF4002
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 6 of 24
R
SET
CP
CPGND
AGND
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RF
IN
B
RF
IN
A
AV
DD
REF
IN
V
P
DV
DD
ADF4002
TOP VIEW
(Not to Scale)
0
PIN 1
INDICATOR
Figure 3. TSSOP (Top View)
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
CPGND 1
AGND 2
AGND 3
RF
IN
B
RF
IN
A
2
A
D
A
D
R
I
D
D
4
5
1
1
1
1
R
S
V
P
D
D
D
D
PIN 1
INDICATOR
ADF4002
TOP VIEW
(Not to Scale)
0
Figure 4. LFCSP_VQ (Top View)
Table 5. Pin Function Descriptions
Pin No.
TSSOP
LFCSP_VQ
1
19
Mnemonic
R
SET
Description
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between
I
CP
and R
SET
is
5
25
=
SET
MAX
CP
R
I
Where
R
SET
= 5.1 kΩ and
I
CP MAX
= 5 mA.
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter that, in turn, drives
the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the RF input.
Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 12.
Input to the RF Input. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to the AV
DD
pin. AV
DD
must be the same value as DV
DD
.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 11. This input can be driven from a TTL or CMOS crystal oscillator or it
can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking this pin high powers up the device, depending on the status of the Power-
Down Bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
Serial Data Input. The serial data is loaded MSB-first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches; the latch is selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
2
20
CP
3
4
5
1
2, 3
4
CPGND
AGND
RF
IN
B
6
7
5
6, 7
RF
IN
A
AV
DD
8
8
REF
IN
9
10
9, 10
11
DGND
CE
11
12
CLK
12
13
DATA
13
14
LE
14
15
MUXOUT
15
16, 17
DV
DD
16
18
V
P
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