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參數(shù)資料
| 型號： | ADE7768AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Energy Metering IC with Integrated Oscillator and Positive Power Accumulation |
| 中文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | PLASTIC, MS-012-AC, SOIC-16 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 299K |
| 代理商： | ADE7768AR |
ADE7768
Typical Connection Diagrams
Figure 20 shows a typical connection diagram for Channel V1.
A shunt is the current sensor selected for this example because
of its low cost compared to other current sensors, such as the
current transformer (CT). This IC is ideal for low current
meters.
R
F
Rev. A | Page 12 of 20
V1P
V1N
C
F
C
F
R
F
±
30mV
SHUNT
AGND
PHASE
NEUTRAL
0
Figure 20. Typical Connection for Channel V1
Figure 21 shows a typical connection for Channel V2. Typically,
the ADE7768 is biased around the phase wire, and a resistor
divider is used to provide a voltage signal that is proportional to
the line voltage. Adjusting the ratio of R
A
, R
B
, and R
convenient way of carrying out a gain calibration on a meter.
F
is also a
V2P
V2N
C
F
PHASE
NEUTRAL
R
F
±
165mV
C
F
R
F
R
B
R
A
*
*R
A
>>
R
B
+ R
F
0
Figure 21. Typical Connections for Channel V2
POWER SUPPLY MONITOR
The ADE7768 contains an on-chip power supply monitor.
The power supply (V
DD
) is continuously monitored by the
ADE7768. If the supply is less than 4 V, the ADE7768 becomes
inactive. This is useful to ensure proper device operation at
power-up and power-down. The power supply monitor has
built-in hysteresis and filtering, which provide a high degree
of immunity to false triggering from noisy supplies.
In Figure 22, the trigger level is nominally set at 4 V. The toler-
ance on this trigger level is within ±5%. The power supply and
decoupling for the part should be such that the ripple at V
DD
does not exceed 5 V ± 5%, as specified for normal operation.
V
DD
5V
4V
0V
TIME
INACTIVE
ACTIVE
INACTIVE
INTERNAL
ACTIVATION
0
Figure 22. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 23 shows the effect of offsets on the real power calcula-
tion. As can be seen, offsets on Channel V1 and Channel V2
contribute a dc component after multiplication. Because this dc
component is extracted by the LPF and used to generate the real
power information, the offsets contribute a constant error to the
real power calculation. This problem is easily avoided by the
built-in HPF in Channel V1. By removing the offsets from at
least one channel, no error component can be generated at dc
by the multiplication. Error terms at the line frequency (ω) are
removed by the LPF and the digital-to-frequency conversion
(see the Digital-to-Frequency Conversion section).
Equation 6 shows how the power calculation is affected by the
dc offsets in the current and voltage channels.
(
)
cos
{
}
cos
{
OS
I
V
t
V
(
)
}
OS
I
t
+
ω
×
+
ω
(6)
(
)
(
)
t
V
I
t
I
V
I
V
I
V
OS
OS
OS
OS
ω
×
+
ω
×
+
×
+
×
2
=
cos
cos
(
)
t
I
V
ω
×
×
2
+
2
cos
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
I
OS
×
V
V
OS
×
I
V
OS
×
I
OS
V
×
I
2
0
FREQUENCY (RAD/s)
0
Figure 23. Effect of Channel Offset on the Real Power Calculation
The HPF in Channel V1 has an associated phase response that
is compensated for on chip. Figure 24 and Figure 25 show the
phase error between channels with the compensation network
activated. The ADE7768 is phase compensated up to 1 kHz as
shown. This ensures correct active harmonic power calculation
even at low power factors.
FREQUENCY (Hz)
0.30
P
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
0
100
200
300
400
500
600
700
800
900 1000
0
Figure 24. Phase Error Between Channels (0 Hz to 1 kHz)
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