參數(shù)資料
型號(hào): ADE7768
廠商: Analog Devices, Inc.
英文描述: Energy Metering IC with Integrated Oscillator and Positive Power Accumulation
中文描述: 電能計(jì)量IC整合的振蕩器和積累的積極力量
文件頁(yè)數(shù): 14/20頁(yè)
文件大小: 299K
代理商: ADE7768
ADE7768
Rev. A | Page 14 of 20
CF
TIME
±
10%
FRRIPPLE
FRAVERAGE
ADE7768
COUNTER
TIMER
MCU
CF
0
Figure 27. Interfacing the ADE7768 to an MCU
As shown in Figure 27, the frequency output CF is connected
to an MCU counter or port. This counts the number of pulses
in a given integration time, which is determined by an MCU
internal timer. The average power proportional to the average
frequency is given by
Time
Counter
Power
Average
Frequency
Average
=
=
(8)
The energy consumed during an integration period is given by
)
Counter
Time
Time
Counter
Time
Power
Average
Energy
=
×
=
×
=
For the purpose of calibration, this integration time could be
10 seconds to 20 seconds, to accumulate enough pulses to
ensure correct averaging of the frequency. In normal operation,
the integration time could be reduced to 1 second or 2 seconds,
depending, for example, on the required update rate of a
display. With shorter integration times on the MCU, the
amount of energy in each update may still have some small
amount of ripple, even under steady load conditions. However,
over a minute or more the measured energy has no ripple.
Power Measurement Considerations
Calculating and displaying power information always has some
associated ripple, which depends on the integration period used
in the MCU to determine average power and also on the load.
For example, at light loads, the output frequency may be 10 Hz.
With an integration period of 2 seconds, only about 20 pulses
are counted. The possibility of missing one pulse always exists,
because the ADE7768 output frequency is running asynchro-
nously to the MCU timer. This results in a 1-in-20 or 5% error
in the power measurement. When REVP is logic high, the
ADE7768 does not generate any pulse on F1, F2, and CF.
INTERNAL OSCILLATOR (OSC)
The nominal internal oscillator frequency is 450 kHz when
used with RCLKIN, with a nominal value of 6.2 kΩ. The
frequency outputs are directly proportional to the oscillator
frequency, thus RCLKIN must have low tolerance and low
temperature drift to ensure stability and linearity of the chip.
The oscillator frequency is inversely proportional to the
RCLKIN, as shown in Figure 28. Although the internal
oscillator operates when used with RCLKIN values between
5.5 kΩ and 20 kΩ, choosing a value within the range of the
nominal value, as shown in Figure 28, is recommended.
RESISTANCE (k
Ω)
5.8
5.9
6.1
6.3
6.7
F
420
430
440
450
460
480
470
490
6.0
6.2
6.4
6.5
6.6
410
400
0
Figure 28. Effect of RCLKIN on Internal Oscillator Frequency (OSC)
TRANSFER FUNCTION
Frequency Outputs F1 and F2
The ADE7768 calculates the product of two voltage signals
(on Channel V1 and Channel V2) and then low-pass filters this
product to extract positive-only real power information. This
positive-only real power information is then converted to a
frequency. The frequency information is output on F1 and F2
in the form of active low pulses. The pulse rate at these outputs
is relatively low—for example, 0.175 Hz maximum for ac signals
with S0 = S1 = 0 (see Table 6). This means that the frequency at
these outputs is generated from positive-only real power
information accumulated over a relatively long period of time.
The result is an output frequency that is proportional to the
average positive-only real power. The averaging of the positive-
only real power signal is implicit to the digital-to-frequency
conversion. The output frequency or pulse rate is related to the
input voltage signals by the following equation:
75
.
494
rms
rms
V
2
REF
4
1
F
V2
V1
Freq
×
×
×
=
(10)
where:
Freq
is the output frequency on F1 and F2 (Hz).
V1
rms
is the differential rms voltage signal on Channel V1 (V).
V2
rms
is the differential rms voltage signal on Channel V2 (V).
V
REF
is the reference voltage (2.45 V ± 200 mV) (V).
F
1–4
are one of four possible frequencies selected by using the
S0 and S1 logic inputs (see Table 5).
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