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ADE7758
INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A)
The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7758, the
corresponding flag in the interrupt status register is set logic high. The IRQ pin goes active low if the corresponding bit in the interrupt
mask register is set logic high. When the MCU services the interrupt, it must first carry out a read from the interrupt status register to
determine the source of the interrupt. All the interrupts in the interrupt status register stay at their logic high state after an event occurs.
The state of the interrupt bit in the interrupt status register is reset to its default value once the reset interrupt status register is read.
Table 20. Interrupt Status Register
Bit Location
Interrupt Flag
Default Value
Event Description
Indicates that an interrupt was caused by a change in Bit 14 among any one of the
three WATTHR registers, i.e., the WATTHR register is half full.
Indicates that an interrupt was caused by a change in Bit 14 among any one of the
three VARHR registers, i.e., the VARHR register is half full.
Indicates that an interrupt was caused by a 0-to-1 transition in Bit 15 among any one
of the three VAHR registers, i.e., the VAHR register is half full.
3
SAGA
0
Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A.
4
SAGB
0
Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B.
5
SAGC
0
Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage
of the Phase A.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage
of the Phase B.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage
of the Phase C.
9
ZXA
0
Indicates a detection of a rising edge zero crossing in the voltage channel of the Phase A.
10
ZXB
0
Indicates a detection of a rising edge zero crossing in the voltage channel of the Phase B.
11
ZXC
0
Indicates a detection of a rising edge zero crossing in the voltage channel of the Phase C.
In line energy accumulation, it indicates the end of an integration over an integer
number of half-line cycles (LINECYC), see the Calibration section.
Indicates that the 5 V power supply is below 4 V. Enables a software reset of the
ADE7758 and sets the registers back to their default values. This bit in the STATUS or
RSTATUS register is logic high for only one clock cycle after a reset event.
Indicates that an interrupt was caused when the selected voltage input is above the
value in the PKVLVL register.
Indicates that an interrupt was caused when the selected current input is above the
value in the PKILVL register.
16
WFSM
0
Indicates that new data is present in the waveform register.
Indicates that an interrupt was caused by a sign change in the watt calculation among
any one of the phases specified by the TERMSEL bits in the COMPMODE register.
Indicates that an interrupt was caused by a sign change in the VAR calculation among
any one of the phases specified by the TERMSEL bits in the COMPMODE register.
Indicates that an interrupt was caused by a zero crossing from Phase A not followed
by the zero crossing of Phase C but by that of Phase B.
Rev. A | Page 66 of 68
0
AEHF
0
1
REHF
0
2
VAEHF
0
6
ZXTOA
0
7
ZXTOB
0
8
ZXTOC
0
12
LENERGY
0
13
RESET
1
14
PKV
0
15
PKI
0
17
REVPAP
0
18
REVPRP
0
19
SEQERR
0