參數(shù)資料
型號: ADE7758ARWZ
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調(diào)理
英文描述: Poly Phase Multifunction Energy Metering IC with Per Phase Information
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: LEAD FREE, MS-013-AD, SOIC-24
文件頁數(shù): 11/68頁
文件大?。?/td> 1584K
代理商: ADE7758ARWZ
ADE7758
Pin No.
17
Rev. A | Page 11 of 68
Mnemonic Description
VARCF
Reactive Power Calibration Frequency Logic Output. It gives reactive power or apparent power information
depending on the setting of the VACF bit of the WAVMODE register. This output is used for operational and
calibration purposes. The full-scale output frequency can be scaled by writing to the VARCFNUM and
VARCFDEN registers (see the Reactive Power Frequency Output section).
Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include: active
energy register at half level, apparent energy register at half level, and waveform sampling up to 26 kSPS (see
the ADE7758 Interrupts section).
Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.
Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock
source for the ADE7758. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of a
few tens of picofarad should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data
sheet for the load capacitance requirements
A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for the
ADE7758. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a
crystal is being used.
Chip Select. Part of the 4-wire serial interface. This active low logic input allows the ADE7758 to share the serial
bus with several other devices (see the ADE7758 Serial Interface section).
Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK (see the ADE7758
Serial Interface section).
Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock
(see the ADE7758 Serial Interface section). The SCLK has a Schmidt-trigger input for use with a clock source
which has a slow edge transition time, for example, opto-isolator outputs.
Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output
is normally in a high impedance state, unless it is driving data onto the serial data bus (see the ADE7758 Serial
Interface section).
18
IRQ
19
CLKIN
20
CLKOUT
21
CS
22
DIN
23
SCLK
24
DOUT
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