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參數(shù)資料
| 型號(hào)： | ADE7757ARN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Energy Metering IC with Integrated Oscillator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | PLASTIC, MS-012AC, SOIC-16 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 534K |
| 代理商： | ADE7757ARN |
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PRELIMINARY TECHNICAL DATA
ADE7757–SPECIFICATIONS
Parameter
REV. PrC.
–2–
(V
DD
= 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, r
CKLIN
= 5 k
0.1
% 5ppm/°C
,
T
MIN
to T
MAX
= –40 C to +85 C)
Value
Units
Test Conditions/Comments
ACCURACY
1, 2
Measurement Error
1
on Channel V1
Channel V2 with Full-Scale Signal (±165 mV),+25°C
% Reading typ Over a Dynamic Range 500 to 1
Line Frequency = 45 Hz to 65 Hz
TBD
Phase Error
1
Between Channels
V1 Phase Lead 37°
(PF = 0.8 Capacitive)
V1 Phase Lag 60°
(PF = 0.5 Inductive)
AC Power Supply Rejection
1
Output Frequency Variation (CF)
±0.1
Degrees(°) max
±0.1
Degrees(°) max
S0 = S1 = 1,
TBD
% Reading typ V1 = V2 = 100 mV rms, @50 Hz
Ripple on V
DD
of 200 mV rms @ 100 Hz
S0 = S1 = 1,
% Reading typ V1 = 100 mV rms, V2 = 100 mV rms,
V
DD =
5 V ±250 mV
DC Power Supply Rejection
1
Output Frequency Variation (CF)
TBD
ANALOG INPUTS
Channel V1 Maximum Signal Level
Channel V2 Maximum Signal Level
Input Impedance (DC)
Bandwidth (–3 dB)
ADC Offset Error
1, 2
Frequency Output Error
1
See Analog Inputs Section
V1P and V1N to AGND
V2N and V2P to AGND
r
CKLIN
= 5 k
0.1
% 5ppm/°C
r
CKLIN
= 5 k
0.1
% 5ppm/°C
See Terminology and Performance Graphs
External 2.5 V Reference,
V1 = 30 mV DC, V2 = 165 mV dc
External 2.5 V Reference, Gain = 1
V1 = 30 mV dc, V2 = 165 mV dc
± 30
±165
TBD
7
±25
TBD
mV max
mV max
k
min
kHz typ
mV max
% Ideal typ
Gain Error
1
±7
% Ideal typ
REFERENCE INPUT
REF
IN/OUT
Input Voltage Range
2.7
2.3
TBD
10
V max
V min
k
min
pF max
2.5 V + 8%
2.5 V – 8%
Input Impedance
Input Capacitance
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
Nominal 2.5 V
±200
30
mV max
ppm/°C typ
ppm/°C max
LOGIC INPUTS
3
SCF, S0, S1,
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
LOGIC OUTPUTS
3
F1 and F2
Output High Voltage, V
OH
2.4
0.8
±3
10
V min
V max
μA max
pF max
V
DD
= 5 V ± 5%
V
DD
= 5 V ± 5%
Typically 10 nA, V
IN
= 0 V to V
DD
I
SOURCE
= 10 mA
V
DD
= 5 V
I
SINK
= 10 mA
V
DD
= 5 V
4.5
V min
Output Low Voltage, V
OL
0.5
V max
CF
Output High Voltage, V
OH
I
SOURCE
= 5 mA
V
DD
= 5 V
I
SINK
= 5 mA
V
DD
= 5 V
4
V min
Output Low Voltage, V
OL
0.5
V max
POWER SUPPLY
V
DD
For Specified Performance
5 V – 5%
5 V + 5%
TBD
4.75
5.25
TBD
V min
V max
TBD
I
DD
NOTES
1
See Terminology Section for explanation of specifications.
2
See Plots in Typical Performance Graphs.
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
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