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參數(shù)資料
| 型號： | ADE7757 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Energy Metering IC with Integrated Oscillator |
| 中文描述： | 電能計量IC集成振蕩器 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 534K |
| 代理商： | ADE7757 |
PRELIMINARY TECHNICAL DATA
REV. PrC.
ADE7757
–10–
POWER SUPPLY MONITOR
The ADE7757 contains an on-chip power supply monitor.
The power supply (V
DD
) is continuously monitored by the
ADE7757. If the supply is less than 4 V, the ADE7757
will reset. This is useful to ensure proper device operation
at power-up and power-down. The power supply monitor
has built in hysteresis and filtering that provide a high
degree of immunity to false triggering from noisy sup-
plies.
As can be seen from Figure 17, the trigger level is nomi-
nally set at 4 V. The tolerance on this trigger level is
within ±5%. The power supply and decoupling for the
part should be such that the ripple at V
DD
does not exceed
5 V ± 5% as specified for normal operation.
V
DD
5V
4V
0V
INTERNAL
ACTIVATION
INACTIVE
TIME
ACTIVE
INACTIVE
Figure 17. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 18 illustrates the effect of offsets on the real power cal-
culation. As can be seen, offsets on Channel V1 and Channel
V2 will contribute a dc component after multiplication. Since
this dc component is extracted by the LPF and used to gener-
ate the real power information, the offsets will contribute a
constant error to the real power calculation. This problem is
easily avoided by the built-in HPF in Channel V1. By removing
the offsets from at least one channel, no error component can
be generated at dc by the multiplication. Error terms at the line
frequency (
ω)
are removed by the LPF and the digital-to-
frequency conversion
—
see Digital-to-Frequency Conver-
sion.
The equation below shows how power calculation is affected by
the dc offsets in the current and voltage channels:
{
V
} {
×
}
)
2
cos(
2
I
V
)
cos(
V
I
)
cos(
I
V
I
V
2
I
I
)
cos(
I
V
t)
Vcos(
×
os
os
os
os
os
os
ω
×
×
+
ω
×
+
ω
×
+
×
+
=
+
ω
+
ω
DC COMPONENT (INCLUDING ERROR TERM) IS
EXTRACTED BY THE LPF FOR REAL POWER CALCULATION
FREQUENCY - Rad/s
0
2
I
V
×
os
os
I
V
×
V
I
os
×
I
V
os
×
Figure 18. Effect of Channel Offset on the Real Power
Calculation
The HPF in Channel V1 has an associated phase response
that is compensated for on-chip. Figures 19 and 20 show
the phase error between channels with the compensation
network activated. The ADE7757 is phase compensated up
to 1 kHz as shown. This will ensure correct active har-
monic power calculation even at low power factors.
FREQUENCY - Hz
0
100
P
-0.05
-0.10
0
0.05
0.10
0.15
0.20
0.25
0.30
200
300
400
500
600
700
800
900
1000
Figure 19. Phase Error Between Channels (0 Hz to 1 kHz)
FREQUENCY - Hz
40
P
-0.05
-0.10
0
0.05
0.10
0.15
0.20
0.25
0.30
45
50
55
60
65
70
Figure 20. Phase Error Between Channels (40 Hz to 70 Hz)
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