- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373980 > ADE7753ARS (ANALOG DEVICES INC) Active and Apparent Energy Metering IC with di/dt sensor interface PDF資料下載
參數(shù)資料
| 型號： | ADE7753ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Active and Apparent Energy Metering IC with di/dt sensor interface |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封裝： | MO-150AE, SSOP-20 |
| 文件頁數(shù)： | 12/38頁 |
| 文件大小： | 449K |
| 代理商： | ADE7753ARS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
ADE7753
–12–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
POWE R SUPPLY MONIT OR
T he ADE7753 also contains an on-chip power supply moni-
tor. T he Analog Supply (AV
DD
) is continuously monitored
by the ADE7753. If the supply is less than 4V ± 5% then the
ADE7753 will go into an inactive state, i.e. no energy will be
accumulated when the supply voltage is below 4V. T his is
useful to ensure correct device operation at power up and
during power down. T he power supply monitor has built-in
hysteresis and filtering. T his gives a high degree of immunity
to false triggering due to noisy supplies.
Time
AVDD
0V
4V
5V
ADE7753
Power-on
Inactive
State
Inactive
Active
Inactive
SAG
Figure 12 - On-Chip power supply monitor
As can be seen from Figure 12 the trigger level is nominally
set at 4V. T he tolerance on this trigger level is about ±5%.
T he
SAG
pin can also be used as a power supply monitor
input to the MCU. T he
SAG
pin will go logic low when the
ADE7753 is in its inactive state. T he power supply and
decoupling for the part should be such that the ripple at
AV
DD
does not exceed 5V±5% as specified for normal
operation.
LINE VOLT AGE SAG DE T E C T ION
In addition to the detection of the loss of the line voltage
signal (zero crossing), the AD E 7753 can also be pro-
grammed to detect when the absolute value of the line voltage
drops below a certain peak value, for a number of line cycles.
T his condition is illustrated in Figure 13 below.
SAGCYC[7:0] = 06H
6 half cycles
SAGLVL[7:0]
Full Scale
Channel 2
SAG
SAG reset high
when Channel 2
exceeds SAGLVL[7:0]
Figure 13– ADE7753 Sag detection
Figure 13 shows the line voltage fall below a threshold which
is set in the Sag Level register (SAGLVL[7:0]) for five line
cycles. Since the Sag Cycle register (SAGCY C[7:0]) con-
tains 03h the
SAG
pin will go active low at the end of the fifth
line cycle for which the line voltage falls below the threshold,
if the DISSAG bit in the Mode register is logic zero. As is
the case when zero-crossings are no longer detected, the sag
event is also recorded by setting the SAG flag in the Interrupt
Status register. If the SAG enable bit is set to logic one, the
IRQ
logic output will go active low - see
ADE7753 Interrupts
.
T he
SAG
pin will go logic high again when the absolute value
of the signal on Channel 2 exceeds the sag level set in the Sag
Level register. T his is shown in Figure 13 when the
SAG
pin
goes high during the tenth line cycle from the time when the
signal on Channel 2 first dropped below the threshold level.
Sag Level Set
T he contents of the Sag Level register (1 byte) are compared
to the absolute value of the most significant byte output from
LPF1, after it is shifted left by one bit. T hus for example the
nominal maximum code from LPF1 with a full scale signal
on Channel 2 is 2518h—see
Channel 2 sampling
. Shifting one
bit left will give 4A30h. T herefore writing 4Ah to the SAG
Level register will put the sag detection level at full scale.
Writing 00h will put the sag detection level at zero. T he Sag
Level register is compared to the most significant byte of a
waveform sample after the shift left and detection is made
when the contents of the sag level register are greater.
PE AK DE T E CT ION
T he ADE7753 can also be programmed to detect when the
absolute value of the voltage or the current channel of one
phase exceeds a certain peak value. Figure 14 illustrates the
behavior of the peak detection for the voltage channel.
VPKLVL[7:0]
V2
PKV Interrupt Flag
(Bit 8 of STATUS register)
PKV reset low
when RSTSTATUS register
is read
Read RSTSTATUS register
Figure 14 - ADE7753 Peak detection
Both channel 1 and channel 2 are monitored at the same time.
Figure 14 shows a line voltage exceeding a threshold which
is set in the Voltage peak register (VPK L VL [7:0]). T he
Voltage Peak event is recorded by setting the PK V flag in the
Interrupt Status register. If the PK V enable bit is set to logic
one in the Interrupt Mask register, the
IRQ
logic output will
go active low. Similarly, the Current Peak event is recorded
by setting the PK I flag in the Ineterrupt Status register—see
ADE7753 Interrupts
.
Peak Level Set
T he contents of the VPK L VL and IPK L VL registers are
respectively compared to the absolute value of channel 1 and
channel 2, after they are multiplied by 2.
相關PDF資料 |
PDF描述 |
|---|---|
| ADE7753ARSRL | Active and Apparent Energy Metering IC with di/dt sensor interface |
| ADE7754 | ADE7754 |
| ADE7754AR | ADE7754 |
| ADE7754ARRL | ADE7754 |
| ADE7755AN-REF | Energy Metering IC with Pulse Output |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADE7753ARSRL | 制造商:Analog Devices 功能描述:Single Phase Multifunction Metering IC 20-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADE7753ARSZ | 功能描述:IC ENERGY METERING 1PHASE 20SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 能量測量 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:* |
| ADE7753ARSZ | 制造商:Analog Devices 功能描述:ENERGY METERING IC |
| ADE7753ARSZ | 制造商:Analog Devices 功能描述:IC MULTIFUNCTION METER |
| ADE7753ARSZRL | 功能描述:IC ENERGY METERING 1PHASE 20SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 能量測量 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:* |
發(fā)布緊急采購，3分鐘左右您將得到回復。