參數(shù)資料
型號(hào)： ADD8608A8A-75BA
廠商： ADATA Technology Co., Ltd.
英文描述： Double Data Rate SDRAM
中文描述： 雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 2/9頁(yè)
文件大?。?/td> 549K
代理商： ADD8608A8A-75BA
A-Data
ADD8608A8A
Double Data Rate SDRAM
8M x 8 Bit x 4 Banks
General Description
The ADD8608A8A are four-bank Double Data
Rate(DDR) Synchronous DRAMs organized as
8,392,608 words x 8 bits x 4 banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Data outputs occur at both rising edges of CK and
/CK.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Ordering Information.
Features
2.5V for VDDQ power supply
SSTL_2 interface
MRS Cycle with address key programs
-CAS Latency (2, 2.5)
-Burst Length (2,4 &8)
-Burst Type (sequential & Interleave)
4 banks operation
Differential clock input (CK, /CK) operation
Double data rate interface
Auto & Self refresh
8192 refresh cycle
DQM for masking
Package:66-pins 400 mil TSOP-Type II
Part No.
Frequency
133Mhz(7.5ns/CL=2)
133Mhz(7.5ns/CL=2.5)
Interface
Package
ADD8608A8A-75BA
ADD8608A8A-75B
SSTL_2
400mil 66pin TSOPII
Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DD
DQ0
V
DDQ
NC
DQ1
V
S S Q
NC
DQ2
V
DDQ
NC
DQ3
V
S S Q
NC
C
V
DDQ
NC
V
DD
NC1
NC
6
65
6
6
4
3
62
61
60
5 9
5 8
5 7
56
55
54
5 3
52
5 1
5 0
4 9
4 8
47
46
4 5
44
V
S S
DQ7
V
S SQ
NC
DQ6
V
DDQ
NC
DQ5
V
S SQ
NC
DQ4
V
DDQ
NC
N C
V
S S Q
DQS
N C
V
V
S S
WE
CAS
RAS
CS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A 6
A5
A4
V
S S
R E F
NC
BS0
BS1
A10/AP
A0
A1
A2
A3
34
35
3 6
37
3 8
39
NC
40
41
42
43
6
7
DD
V
66-pin plastic TSOP II 400 mil
Rev 2 April, 2002
2
相關(guān)PDF資料
PDF描述
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