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參數(shù)資料
| 型號(hào)： | ADCMP604BKSZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP TTL/CMOS 1CHAN SC70-6 |
| 標(biāo)準(zhǔn)包裝： | 10,000 |
| 類型： | 通用 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補(bǔ)充型，LVDS，滿擺幅 |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 3V |
| 電流 - 輸入偏壓（最小值）： | 5µA @ 3V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 50mA |
| 電流 - 靜態(tài)（最大值）： | 21mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 50dB CMRR，50dB PSRR |
| 傳輸延遲（最大）： | 3ns |
| 磁滯： | 100µV |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
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ADCMP604/ADCMP605
Rev. A | Page 12 of 16
The hysteresis control pin appears as a 1.25 V bias voltage
seen through a series resistance of 70 kΩ ± 20% throughout the
hysteresis control range. The advantages of applying hysteresis
in this manner are improved accuracy, improved stability, reduced
component count, and maximum versatility. An external bypass
capacitor is not recommended on the HYS pin because it would
likely degrade the jitter performance of the device and impair the
latch function. As described in the Using/Disabling the Latch
Feature section, hysteresis control need not compromise the
latch function.
0
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250
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100
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HYSTERESIS RESISTOR (k)
H
Y
ST
E
R
ES
IS
(
m
V
)
VCC = 2.5V
VCC = 5.5V
05
91
6-
0
26
Figure 20. Hysteresis vs. RHYS Control Resistor
CROSSOVER BIAS POINTS
Rail-to-rail inputs of this type, in both op amps and comparators,
have a dual front-end design. Certain devices are active near
the VCCI rail and others are active near the VEE rail. At some pre-
determined point in the common-mode range, a crossover
occurs. At this point, normally VCCI/2, the direction of the bias
current reverses and there are changes in measured offset
voltages and currents.
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PCB design
practice, as discussed in the Optimizing Performance section,
these comparators should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the violent chattering seen with most other high
speed comparators. With additional capacitive loading or poor
bypassing, oscillation is observed. This oscillation is due to the
high gain bandwidth of the comparator in combination with
feedback parasitics in the package and PCB. In many applications,
chattering is not harmful.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCMP604BKSZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP605 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP605BCPZ-R2 | 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP605BCPZ-R21 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP605BCPZ-R7 | 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標(biāo)準(zhǔn)）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標(biāo)準(zhǔn)）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
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