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參數(shù)資料
| 型號： | ADCMP603BCPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP TTL/CMOS 1CHAN 12-LFCSP |
| 標準包裝： | 1 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | CMOS，補充型，滿擺幅，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 2.5V |
| 電流 - 輸入偏壓（最小值）： | 5µA @ 2.5V |
| 電流 - 輸出（標準）： | 50mA |
| 電流 - 靜態(tài)（最大值）： | 1.8mA |
| CMRR, PSRR（標準）： | 50dB CMRR，50dB PSRR |
| 傳輸延遲（最大）： | 5ns |
| 磁滯： | 100µV |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 12-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 765 (CN2011-ZH PDF) |
| 其它名稱： | ADCMP603BCPZ-R7DKR |
ADCMP603
Rev. 0 | Page 5 of 16
TIMING INFORMATION
Figure 2 illustrates the ADCMP603 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
50%
VN ± VOS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
tH
tPDL
tPLOH
tF
VIN
VOD
tS
tPL
05
91
5
-02
3
50%
Q OUTPUT
tPDH
tPLOL
tR
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
Description
t
Input to output high delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
PDH
t
Input to output low delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
PDL
t
Latch enable to output high delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
PLOH
t
Latch enable to output low delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
PLOL
t
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
H
t
Minimum latch enable pulse width
Minimum time that the latch enable signal must be high to acquire an input signal change.
PL
t
Minimum setup time
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
S
t
Output rise time
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
R
t
Output fall time
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
F
V
Voltage overdrive
Difference between the input voltages V
OD
A
and V .
B
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADCMP603BCPZ-WP | 功能描述:IC COMP TTL/CMOS 1CHAN 12-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP604 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP604_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP604BKSZ | 制造商:Analog Devices 功能描述:COMPARATOR SGL R-R I/P 5.5V 6PIN SC-70 - Bulk |
| ADCMP604BKSZ-R2 | 功能描述:IC COMP TTL/CMOS 1CHAN SC70-6 RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標準包裝:1 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標準）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標準）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
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