參數(shù)資料
型號(hào)： ADCMP580BCPZ-WP
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 12/16頁(yè)
文件大?。?/td> 0K
描述： IC COMPARATOR CML UFAST 16-LFCSP
標(biāo)準(zhǔn)包裝： 50
類(lèi)型： 帶鎖銷(xiāo)
元件數(shù)： 1
輸出類(lèi)型： CML，補(bǔ)充型
電壓 - 電源，單路/雙路(±)： ±4.5 V ~ 5.5 V
電壓 - 輸入偏移（最小值）： 10mV @ ±5V
電流 - 輸入偏壓（最小值）： 30µA @ ±5V
電流 - 輸出（標(biāo)準(zhǔn)）： 44mA @ 5V
電流 - 靜態(tài)（最大值）： 8mA
CMRR, PSRR（標(biāo)準(zhǔn)）： 60dB CMRR，75dB PSRR
傳輸延遲（最大）： 0.18ns
磁滯： 1mV
工作溫度： -40°C ~ 125°C
封裝/外殼： 16-VFQFN 裸露焊盤(pán)，CSP
安裝類(lèi)型： 表面貼裝
包裝： 托盤(pán) - 晶粒
產(chǎn)品目錄頁(yè)面： 764 (CN2011-ZH PDF)
ADCMP580/ADCMP581/ADCMP582
Rev. A | Page 5 of 16
TIMING INFORMATION
Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the
terms shown in Figure 2.
50%
VN ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VN
VOD
tS
tPL
04672-028
Figure 2. Comparator Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
Description
tPDH
Input-to-Output High Delay
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
Input-to-Output Low Delay
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high-to-low transition.
tPLOH
Latch Enable-to-Output High Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL
Latch Enable-to-Output Low Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tH
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
tPL
Minimum Latch Enable Pulse Width
Minimum time that the latch enable signal must be high to acquire an input signal change.
tS
Minimum Setup Time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
tR
Output Rise Time
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
tF
Output Fall Time
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
VN
Normal Input Voltage
Difference between the input voltages VP and VN for output true.
VOD
Voltage Overdrive
Difference between the input voltages VP and VN for output false.
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