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| 型號(hào)： | ADCMP572BCP-RL7 |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators |
| 中文描述： | COMPARATOR, 5000 uV OFFSET-MAX, 0.165 ns RESPONSE TIME, QCC16 |
| 封裝： | 3 X 3 MM, MO-220-VEED-2, LFCSP-16 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 381K |
| 代理商： | ADCMP572BCP-RL7 |
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ADCMP572/ADCMP573
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP572/ADCMP573 comparators are very high speed
SiGe devices. Consequently, it is essential to use proper high
speed design techniques to achieve the specified performance.
Of critical importance is the use of low impedance supply
planes, particularly the output supply plane (V
CCO
) and the
ground plane (GND). Individual supply planes are recom-
mended as part of a multilayer board. Providing the lowest
inductance return path for switching currents ensures the best
possible performance in the target application.
Rev. 0 | Page 9 of 16
It is important to adequately bypass the input and output
supplies. A 1 μF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the V
CCI
and V
CCO
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be avoided to maximize the
effectiveness of the bypass at high frequencies.
If the input and output supplies are connected separately such
that V
CCI
≠ V
CCO
, care should be taken to bypass each of these
supplies separately to the GND plane. A bypass capacitor should
not be connected between them. It is recommended that the
GND plane separate the V
CCI
and V
CCO
planes when the circuit
board layout is designed to minimize coupling between the two
supplies and to take advantage of the additional bypass capaci-
tance from each respective supply to the ground plane. This
enhances the performance when split input/output supplies are
used. If the input and output supplies are connected together for
single-supply operation such that V
CCI
= V
CCO
, coupling between
the two supplies is unavoidable; however, every effort should be
made to keep the supply plane adjacent to the GND plane to
maximize the additional bypass capacitance this arrangement
provides.
CML/RSPECL OUTPUT STAGE
Specified propagation delay dispersion performance can be
achieved only by using proper transmission line terminations.
The outputs of the ADCMP572 are designed to directly drive
400 mV into 50 cable, microstrip, or strip line transmission
lines properly terminated to the V
CCO
supply plane. The CML
output stage is shown in the simplified schematic diagram of
Figure 15. The outputs are each back terminated with 50 for
best transmission line matching. The RSPECL outputs of the
ADCMP573 are illustrated in Figure 16 and should be
terminated to V
CCO
2 V. As an alternative, Thevenin equivalent
termination networks can be used in either case if the direct
termination voltage is not readily available. If high speed output
signals must be routed more than a centimeter, microstrip or
strip line techniques are essential to ensure proper transition
times and to prevent output ringing and pulse width dependent
propagation delay dispersion. For the most timing critical
applications where transmission line reflections pose the
greatest risk to performance, the ADCMP572 provides the best
match to 50 output transmission paths.
Q
16mA
50
Q
0
V
CCO
GND
Figure 15. Simplified Schematic Diagram of
the ADCMP572 CML Output Stage
0
V
CCO
GND
Q
Q
Figure 16. Simplified Schematic Diagram of
the ADCMP573 RSPECL Output Stage
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/LE) are active low for latch mode and are
internally terminated with 50 resistors to Pin 8. This pin
corresponds to and is internally connected to the V
CCO
supply
for the CML-compatible ADCMP572. With the aid of these
resistors the ADCMP572 latch function can be disabled by
connecting the LE pin to GND with an external pull-down
resistor and leaving the LE pin unconnected. To avoid excessive
power dissipation, the resistor should be 750 when V
CCO
=
3.3 V, and 1.2 k when V
CCO
= 5.2 V. In the PECL-compatible
ADCMP573, the V
TT
pin should be connected externally to the
PECL termination supply at V
CCO
– 2 V. The latch can then be
disabled by connecting the LE pin to V
CCO
with an external
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADCMP572BCP-WP | Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators |
| ADCMP573BCP-R2 | Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators |
| ADCMP573BCP-RL7 | Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators |
| ADCMP573BCP-WP | Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators |
| ADCMP572 | Ultrafast 3.3 V Single-Supply Comparators |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCMP572BCP-WP | 制造商:Analog Devices 功能描述:Comparator Single 5.4V 16-Pin LFCSP EP |
| ADCMP572BCPZ-R2 | 功能描述:IC COMPARATOR CML 3.3-5V 16LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:通用 元件數(shù):1 輸出類(lèi)型:CMOS，開(kāi)路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標(biāo)準(zhǔn)）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標(biāo)準(zhǔn)）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類(lèi)型:表面貼裝 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:1268 (CN2011-ZH PDF) 其它名稱(chēng):*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| ADCMP572BCPZ-RL7 | 功能描述:IC COMPARATOR CML 3.3-5V 16LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:通用 元件數(shù):1 輸出類(lèi)型:CMOS，推挽式，滿(mǎn)擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類(lèi)型:表面貼裝 包裝:管件 其它名稱(chēng):Q3554586 |
| ADCMP572BCPZ-WP | 功能描述:IC COMPARATOR CML 3.3-5V 16LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 線(xiàn)性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類(lèi)型:帶電壓基準(zhǔn) 元件數(shù):4 輸出類(lèi)型:開(kāi)路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標(biāo)準(zhǔn)）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類(lèi)型:表面貼裝 包裝:管件 產(chǎn)品目錄頁(yè)面:1386 (CN2011-ZH PDF) |
| ADCMP572XCP | 制造商:Analog Devices 功能描述:CML ULTRAFAST 3.3V SINGLE SUPPLY COMPARATOR - Bulk |
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