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參數(shù)資料
| 型號： | ADCMP564BRQZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR ECL DUAL HS 20QSOP |
| 標(biāo)準(zhǔn)包裝： | 56 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 2 |
| 輸出類型： | 補(bǔ)充型，差分，ECL，開路發(fā)射極 |
| 電壓 - 電源，單路/雙路(±)： | ±4.75 V ~ 5.25 V |
| 電壓 - 輸入偏移（最小值）： | 2mV @ -5.2V，5V |
| 電流 - 輸入偏壓（最小值）： | 3µA @ -5.2V，5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 5mA，25mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 80dB CMRR，85dB PSRR |
| 傳輸延遲（最大）： | 0.83ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-SSOP（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 764 (CN2011-ZH PDF) |
| 配用： | EVAL-ADCMP564BRQZ-ND - BOARD EVALUATION ADCMP564BRQZ |
ADCMP563/ADCMP564
Rev. C | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04650-
0-
002
ADCMP563
BRQ
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–INA
+INA
QA
GND
VEE
LEA
–INB
+INB
QB
GND
VCC
LEB
Figure 5. ADCMP563 16-Lead QSOP
Pin Configuration
04650-
0-
012
ADCMP564
BRQ
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
–INA
QA
GND
VEE
LEA
GND
+INA
HYSA
–INB
QB
GND
VCC
LEB
GND
+INB
HYSB
Figure 6. ADCMP564 20-Lead QSOP
Pin Configuration
04650-
0
-027
ADCMP563
BCP
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
–INA
VCC LEB LEB GND
VEE LEA LEA GND
+INA
+INB
QB
–INB
QA
QB
PIN1
NOTES:
1. THE EXPOSED PAD SHOULD BE EITHER
CONNECTED TO VEE OR LEFT FLOATING.
Figure 7. ADCMP563 16-Lead LFCSP
Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP563
16-Lead
QSOP
ADCMP563
16-Lead
LFCSP
ADCMP564
20-Lead
QSOP
Mnemonic
Function
1
GND
Analog Ground.
1
11
2
QA
One of Two Complementary Outputs for Channel A. QA is logic high if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See
the description of the LEA pin for more information.
2
12
3
QA
One of Two Complementary Outputs for Channel A. QA is logic low if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See
the description of the LEA pin for more information.
3
13
4
GND
Analog Ground.
4
14
5
LEA
One of Two Complementary Inputs for Channel A Latch Enable. In compare
mode (logic high), the output tracks change at the input of the comparator.
In latch mode (logic low), the output reflects the input state just prior to the
comparator being placed in the latch mode. LEA must be driven in
conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
5
15
6
LEA
One of Two Complementary Inputs for Channel A Latch Enable. In compare
mode (logic low), the output tracks change at the input of the comparator.
In latch mode (logic high), the output reflects the input state just prior to the
comparator being placed in the latch mode. LEA must be driven in
conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
6
16
7
VEE
Negative Supply Terminal.
7
1
8
INA
Inverting Analog Input of the Differential Input Stage for Channel A. The
Inverting A input must be driven in conjunction with the Noninverting A input.
8
2
9
+INA
Noninverting Analog Input of the Differential Input Stage for Channel A. The
Noninverting A input must be driven in conjunction with the Inverting A input.
10
HYSA
Programmable Hysteresis Input.
11
HYSB
Programmable Hysteresis Input.
9
3
12
+INB
Noninverting Analog Input of the Differential Input Stage for Channel B. The
Noninverting B input must be driven in conjunction with the Inverting B input.
10
4
13
INB
Inverting Analog Input of the Differential Input Stage for Channel B. The
Inverting B input must be driven in conjunction with the Noninverting B input.
11
5
14
VCC
Positive Supply Terminal.
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