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參數資料
| 型號： | ADCMP553BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR PECL/LVPECL 8MSOP |
| 標準包裝： | 50 |
| 類型： | 帶鎖銷 |
| 元件數： | 1 |
| 輸出類型： | 補充型，差分，LVPECL，開路發(fā)射極，PECL |
| 電壓 - 電源，單路/雙路(±)： | 3.14 V ~ 5.25 V |
| 電壓 - 輸入偏移（最小值）： | 10mV @ 3.3V |
| 電流 - 輸入偏壓（最小值）： | 28µA @ 3.3V |
| 電流 - 輸出（標準）： | 55mA @ 3.3V |
| 電流 - 靜態(tài)（最大值）： | 13mA |
| CMRR, PSRR（標準）： | 76dB CMRR，70dB PSRR |
| 傳輸延遲（最大）： | 0.625ns |
| 磁滯： | ± 0.5mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 管件 |
| 產品目錄頁面： | 764 (CN2011-ZH PDF) |
| 配用： | EVAL-ADCMP553BRMZ-ND - BOARD EVALUATION ADCMP553BRMZ |
ADCMP551/ADCMP552/ADCMP553
Data Sheet
Rev. A | Page 10 of 16
TIMING INFORMATION
Figure 17. System Timing Diagram
Figure 17 shows the compare and latch features of the ADCMP55x family. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol
Timing
Description
tPDH
Input to Output High Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition
tPDL
Input to Output Low Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition
tPLOH
Latch Enable to Output High Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition
tPLOL
Latch Enable to Output Low Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition
tH
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs
tPL
Minimum Latch Enable Pulse Width
Minimum time the latch enable signal must be high to acquire an input signal change
tS
Minimum Setup Time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs
tR
Output Rise Time
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points
tF
Output Fall Time
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points
VOD
Voltage Overdrive
Difference between the differential input and reference input voltages
50%
VREF ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VIN
VOD
tS
tPL
04722-016
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADCMP553BRMZ | 制造商:Analog Devices 功能描述:IC, HIGH SPEED COMP, SINGLE, 500PS MSOP8 |
| ADCMP561 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual High Speed PECL Comparators |
| ADCMP561BRQ | 功能描述:IC COMP PECL DUAL HS 16-QSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP561BRQZ | 功能描述:IC COMPARATOR PECL DUAL 16QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:帶電壓基準 元件數:4 輸出類型:開路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標準）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產品目錄頁面:1386 (CN2011-ZH PDF) |
| ADCMP562 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual High Speed PECL Comparators |
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