參數(shù)資料
型號(hào)： ADCMP553BRM
廠商： ANALOG DEVICES INC
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Single Supply High Speed PECL Comparators
中文描述： COMPARATOR, 10000 uV OFFSET-MAX, PDSO8
封裝： MO-187AA, MSOP-8
文件頁(yè)數(shù)： 6/14頁(yè)
文件大小： 522K
代理商： ADCMP553BRM
ADCMP551/ADCMP552/ADCMP553
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrB | Page 6 of 14
0
ADCMP551
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–INA
+INA
QA
QA
V
CCO
V
CCI
LEA
LEA
–INB
+INB
QB
QB
V
CCO
AGND
LEB
LEB
0
ADCMP552
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
–INA
QA
QA
V
CCO
V
CCI
LEA
LEA
V
CCO
+INA
HYSA
–INB
QB
QB
V
CCO
AGND
LEB
LEB
V
CCO
+INB
HYSB
0
ADCMP553
TOP VIEW
(Not to Scale)
1
2
3
4
8
7
6
5
LEA
LEA
+INA
–INA
QA
Figure 2. ADCMP551 16-Lead QSOP Pin
Configuration
Figure 3. ADCMP552 20-Lead QSOP Pin
Configuration
Figure 4. ADCMP553 8-Lead MSOP Pin Configuration
Table 3. ADCMP551/ADCMP552/ADCMP553 Pin Function Descriptions
Pin No.
ADCMP551
ADCMP552
ADCMP553
3, 14
1, 4, 17, 20
1
2
6
Mnemonic
V
CCO
QA
Function
Logic Supply Terminal.
One of Two Complementary Outputs for Channel A. QA is logic high if the
analog voltage at the noninverting input is greater than the analog voltage at
the inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
One of Two Complementary Outputs for Channel A. QA is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
prior to the comparator’s being placed in the latch mode. LEA must be driven in
conjunction with LEA.
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
prior to the comparator’s being placed in the latch mode. LEA must be driven in
conjunction with LEA.
Input Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The
inverting A input must be driven in conjunction with the noninverting A input.
Noninverting Analog Input of the Differential Input Stage for Channel A. The
noninverting A input must be driven in conjunction with the inverting A input.
Programmable Hysteresis.
Programmable Hysteresis.
Noninverting Analog Input of the Differential Input Stage for Channel B. The
noninverting B input must be driven in conjunction with the inverting B input.
Inverting Analog Input of the Differential Input Stage for Channel B. The
inverting B input must be driven in conjunction with the noninverting B input.
Analog Ground.
2
3
5
QA
4
5
2
LEA
5
6
1
LEA
6
7
7
8
4
V
CCI
INA
8
9
3
+INA
9
10
11
12
HYSA
HYSB
+INB
10
13
INB
11
14
8
AGND
QA
V
CC
AGND
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADCMP553BRMZ 功能描述:IC COMPARATOR PECL/LVPECL 8MSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，開(kāi)路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標(biāo)準(zhǔn)）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標(biāo)準(zhǔn)）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT
ADCMP553BRMZ 制造商:Analog Devices 功能描述:IC, HIGH SPEED COMP, SINGLE, 500PS MSOP8
ADCMP561 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual High Speed PECL Comparators
ADCMP561BRQ 功能描述:IC COMP PECL DUAL HS 16-QSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586
ADCMP561BRQZ 功能描述:IC COMPARATOR PECL DUAL 16QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:帶電壓基準(zhǔn) 元件數(shù):4 輸出類型:開(kāi)路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標(biāo)準(zhǔn)）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產(chǎn)品目錄頁(yè)面:1386 (CN2011-ZH PDF)
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