- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2064 > ADCLK946BCPZ (Analog Devices Inc)IC CLK BUFFER 1:6 4.8GHZ 24LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADCLK946BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER 1:6 4.8GHZ 24LFCSP |
| 標準包裝： | 1 |
| 系列： | SIGe |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 4.8GHz |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 托盤 |
ADCLK946
Rev. A | Page 9 of 12
FUNCTIONAL DESCRIPTION
CLOCK INPUTS
The ADCLK946 accepts a differential clock input and distributes it
to all six LVPECL outputs. The maximum specified frequency is
the point at which the output voltage swing is 50% of the standard
LVPECL swing (see Figure 4).
The device has a differential input equipped with center-tapped,
differential, 100 on-chip termination resistors. The input accepts
dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and
ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin
is available for biasing ac-coupled inputs (see Figure 1).
Maintain the differential input voltage swing from approximately
400 mV p-p to no more than 3.4 V p-p. See Figure 14 through
Figure 17 for various clock input termination schemes.
Output jitter performance is degraded by an input slew rate
below 1 V/ns, as shown in Figure 12. The ADCLK946 is
specifically designed to minimize added random jitter over a
wide input slew rate range. Whenever possible, clamp excessively
large input signals with fast Schottky diodes because attenuators
reduce the slew rate. Input signal runs of more than a few
centimeters should be over low loss dielectrics or cables with
good high frequency characteristics.
CLOCK OUTPUTS
The specified performance necessitates using proper trans-
mission line terminations. The LVPECL outputs of the
ADCLK946 are designed to directly drive 800 mV into a 50
cable or into microstrip/stripline transmission lines terminated
LVPECL output stage is shown in Figure 13. The outputs are
designed for best transmission line matching. If high speed
signals must be routed more than a centimeter, either the
microstrip or the stripline technique is required to ensure
proper transition times and to prevent excessive output ringing
and pulse-width-dependent, propagation delay dispersion.
VEE
VCC
Q
08053-
013
Figure 13. Simplified Schematic Diagram of
the LVPECL Output Stage
Figure 14 through Figure 17 depict various LVPECL output
termination schemes. When dc-coupled, VCC of the receiving
buffer should match the VS_DRV.
Thevenin-equivalent termination uses a resistor network to
provide 50 termination to a dc voltage that is below VOL of
the LVPECL driver. In this case, VS_DRV on the ADCLK946
should equal VCC of the receiving buffer. Although the resistor
combination shown in Figure 15 results in a dc bias point of
VS_DRV 2 V, the actual common-mode voltage is VS_DRV
1.3 V because there is additional current flowing from the
ADCLK946 LVPECL driver through the pull-down resistor.
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue.
VS_DRV
Z0 = 50
VS = VS_DRV
LVPECL
50
VCC – 2V
50
Z0 = 50
ADCLK946
08053-
014
Figure 14. DC-Coupled, 3.3 V LVPECL
VS_DRV
50
50
SINGLE-ENDED
(NOT COUPLED)
VCC
VS_DRV
LVPECL
127
127
83
83
ADCLK946
08053-
015
Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination
VS_DRV
Z0 = 50
VS = VS_DRV
LVPECL
50
50
50
Z0 = 50
ADCLK946
08053-
016
Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination
VS_DRV
100
DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
VCC
LVPECL
100
0.1nF
200
200
ADCLK946
08053-
017
Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADCLK948BCPZ-REEL7 | IC CLOCK BUFFER MUX 2:8 32-LFCSP |
| ADCLK950BCPZ | IC CLOCK BUFFER MUX 2:10 40LFCSP |
| ADCLK954BCPZ-REEL7 | IC CLOCK BUFFER MUX 2:12 40LFCSP |
| ADCMP343YRJZ-REEL7 | IC COMPARATOR DUAL OD SOT23-8 |
| ADCMP356YKS-REEL7 | IC COMP/REF PP ACTIVE HI SC70-4 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCLK946BCPZ-REEL7 | 功能描述:IC CLK BUFFER 1:6 4.8GHZ 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:SIGe 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ADCLK948 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer |
| ADCLK948/PCBZ | 功能描述:BOARD EVALUATION FOR ADCLK948 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SIGe 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| ADCLK948BCPZ | 功能描述:IC CLOCK BUFFER MUX 2:8 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:SIGe 產(chǎn)品培訓模塊:High Bandwidth Product Overview 標準包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
| ADCLK948BCPZ | 制造商:Analog Devices 功能描述:CLOCK FANOUT BUFFER, 4.8GHZ, LFCSP-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。