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| 型號(hào)： | ADCLK944BCPZ-R2 |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER 1:4 7GHZ 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SIGe |
| 類(lèi)型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，CMOS，LVDS，LVPECL |
| 輸出： | ECL，LVPECL |
| 頻率 - 最大： | 7GHz |
| 電源電壓： | 2.375 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-WQ（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱(chēng)： | ADCLK944BCPZ-R2DKR |
ADCLK944
Rev. 0 | Page 9 of 12
THEORY OF OPERATION
CLOCK INPUTS
The ADCLK944 accepts a differential clock input and distrib-
utes it to all four LVPECL outputs. The maximum specified
frequency is the point at which the output voltage swing is 50%
of the standard LVPECL swing (see Figure 4).
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input can
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended,
3.3 V operation only), and ac-coupled 1.8 V CMOS, LVDS, and
LVPECL inputs. A VREF pin is available for biasing ac-coupled
Maintain the differential input voltage swing from approxi-
mately 400 mV p-p to no more than 3.4 V p-p. See Figure 18
through Figure 21 for various clock input termination schemes.
Output jitter performance is significantly degraded by an input
slew rate below 1 V/ns, as shown in Figure 11. The ADCLK944
is specifically designed to minimize added random jitter over a
wide input slew rate range. Whenever possible, clamp excessively
large input signals with fast Schottky diodes because attenuators
reduce the slew rate. Input signal runs of more than a few centi-
meters should be over low loss dielectrics or cables with good
high frequency characteristics.
CLOCK OUTPUTS
The specified performance necessitates using proper transmis-
sion line terminations. The LVPECL outputs of the ADCLK944
are designed to directly drive 800 mV into a 50 Ω cable or into
microstrip/stripline transmission lines terminated with 50 Ω
output stage is shown in Figure 12. The outputs are designed
for best transmission line matching. If high speed signals must
be routed more than a centimeter, either the microstrip or the
stripline technique is required to ensure proper transition times
and to prevent excessive output ringing and pulse-width-dependent
propagation delay dispersion.
VEE
VCC
Q
08
77
0-
0
1
3
Figure 12. Simplified Schematic Diagram
of the LVPECL Output Stage
termination schemes. When dc-coupled, VCC of the receiving
buffer should match VS_DRV.
ADCLK944
VS_DRV
VCC = VS_DRV
Z0 = 50
LVPECL
50
VCC – 2V
50
08
77
0-
0
1
4
Z0 = 50
Figure 13. DC-Coupled, 3.3 V LVPECL
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below VOL of the LVPECL
driver. In this case, VS_DRV on the ADCLK944 should equal
VCC of the receiving buffer. Although the resistor combination
shown in Figure 14 results in a dc bias point of VS_DRV 2 V,
the actual common-mode voltage is VS_DRV 1.3 V because
there is additional current flowing from the ADCLK944 LVPECL
driver through the pull-down resistor.
VS_DRV
50
50
SINGLE-ENDED
(NOT COUPLED)
VS_DRV
ADCLK944
VCC
LVPECL
127
127
83
83
87
70
-01
5
0
Figure 14. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination
LVPECL Y-termination (see Figure 15) is an elegant termination
scheme that uses the fewest components and offers both odd-
and even-mode impedance matching. Even-mode impedance
matching is an important consideration for closely coupled trans-
mission lines at high frequencies. Its main drawback is that it offers
limited flexibility for varying the drive strength of the emitter-
follower LVPECL driver. This can be an important consideration
when driving long trace lengths but is usually not an issue.
ADCLK944
VS_DRV
VCC = VS_DRV
Z0 = 50
LVPECL
50
50
50
87
70-
0
16
Z0 = 50
0
Figure 15. DC-Coupled, 3.3 V LVPECL Y-Termination
A
VS_DRV
100
DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
VCC
LVPECL
100
0.1nF
DCLK944
200
200
08
77
0-
01
7
Figure 16. AC-Coupled LVPECL with Parallel Transmission Line
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| ADCLK944BCPZ-R7 | 功能描述:IC CLOCK BUFFER 1:4 7GHZ 16LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:SIGe 標(biāo)準(zhǔn)包裝:74 系列:- 類(lèi)型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
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