參數(shù)資料
型號: ADCLK925BCPZ-R2
廠商: Analog Devices Inc
文件頁數(shù): 14/16頁
文件大小: 0K
描述: IC CLOCK/DATA BUFFER 1:2 16LFCSP
標準包裝: 250
系列: SIGe
類型: 扇出緩沖器(分配),數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
輸入: 時鐘
輸出: ECL,NECL,PECL
頻率 - 最大: 7.5GHz
電源電壓: 2.375 V ~ 3.63 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,CSP
供應商設備封裝: 16-LFCSP-VQ
包裝: 帶卷 (TR)
配用: ADCLK925/PCBZ-ND - BOARD EVAL FOR ADCLK925 16LFCSP
ADCLK905/ADCLK907/ADCLK925
Rev. 0 | Page 7 of 16
Pin No.
Mnemonic
Description
10
Q2
Noninverting Output 2.
11
Q1
Inverting Output 1.
12
Q1
Noninverting Output 1.
15
VREF1
Reference Voltage 1. Reference voltage for biasing ac-coupled inputs, Channel 1.
16
VT1
Center Tap 1. Center tap of 100 Ω input resistor, Channel 1.
Heat Sink
NC
No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit.
It can be left floating for optimal electrical isolation between the package handle and the substrate of the die.
It can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance
to vias and other components.
PIN 1
INDICATOR
NC = NO CONNECT
1
D
2
D
3
NC
4
NC
11 Q1
12 Q1
10 Q2
9Q2
5
N
C
6
N
C
7
V
E
8
V
C
15
V
R
E
F
16
V
T
14
V
E
13
V
C
ADCLK925
TOP VIEW
(Not to Scale)
06
31
8-
0
06
Figure 6. ADCLK925 Pin Configuration
Table 6. Pin Function Descriptions for 1:2 ADCLK925 Buffer
Pin No.
Mnemonic
Description
1
D
Noninverting Input.
2
D
Inverting Input.
3, 4, 5, 6
NC
No Connect. No physical connection to the die.
7, 14
VEE
Negative Supply Voltage.
8, 13
VCC
Positive Supply Voltage.
9
Q2
Inverting Output 2.
10
Q2
Noninverting Output 2.
11
Q1
Inverting Output 1.
12
Q1
Noninverting Output 1.
15
VREF
Reference Voltage. Reference voltage for biasing ac-coupled inputs.
16
VT
Center Tap. Center tap of 100 Ω input resistor.
Heat Sink
NC
No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit.
It can be left floating for optimal electrical isolation between the package handle and the substrate of the die.
It can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance
to vias and other components.
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