參數(shù)資料
型號(hào): ADCDS-1403
廠商: CD TECHNOLOGIES INC
元件分類(lèi): ADC
英文描述: 14-Bit, 3 Megapixels/Second Imaging Signal Processor
中文描述: 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, DIP40
封裝: TDIP-40
文件頁(yè)數(shù): 7/9頁(yè)
文件大?。?/td> 198K
代理商: ADCDS-1403
ADCDS -1403
7
Table 3. Programmable Analog Bandwidth
REFERENCE HOLD
"AQUISITION TIME"
CDS OUTPUT
"SETTLING TIME"
A0
A1
ADCDS-1403 MAXIMUM
CONVERSION RATE
(Pin 30)
(Pin 31)
3dB BW
100ns
120ns
0
0
3MHz
10.5MHz
200ns
250ns
1
0
2MHz
6.6MHz
450ns
500ns
0
1
1MHz
3.7MHz
600ns
1000ns
1
1
0.5MHz
2.5MHz
Note: See Figure 11. for timing details
Timing
The ADCDS-1403 requires two independently operated
signals to accurately digitize the analog output signal from the
CCD array.
Reference Hold (pin 26)
Start Convert (pin 25)
The "Reference Hold" signal controls the operation of an
internal sample-hold circuit. A logic "1" places the sample-
hold into the hold mode, capturing the value of the CCD's
Figure 9. ADCDS-1403 Connection Diagram
reference signal. The Reference Hold Signal allows the user
to control the exact moment when the sample-hold is placed
into the "hold" mode. For optimal performance the sample-
hold should be placed into the "hold" mode once the
reference signal has fully settled from all switching
transients to the desired accuracy (user defined).
Once the reference signal has been "held" and the video
portion of the CCD's analog output signal appears at the
ADCDS-1403's input, the ADCDS-1403's correlated double
sampler produces a "CDS Output" signal (see Figure 11.)
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