參數(shù)資料
型號(hào)： ADC912AFP
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： CMOS Microprocessor-Compatible 12-Bit A/D Converter
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP24
封裝： 0.300 INCH, PLASTIC, DIP-24
文件頁(yè)數(shù)： 6/16頁(yè)
文件大小： 237K
代理商： ADC912AFP
REV. B
ADC912A
–6–
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
l
2
3
4 . . . 11
13 . . . 16
AIN
VREFIN
AGND
D
11
. . . D
4
D
3/11
. . . D
0/8
Analog Input. 0 V to 10 V.
Voltage Reference Input. Requires external –5 V reference.
Analog Ground.
Three-state data outputs become active when
CS
and
RD
are brought low.
Individual pin function is dependent upon High Byte Enable (HBEN) input.
DATA BUS OUTPUT,
CS
and
RD
= LOW
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
Mnemonic
*
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3/11
D
2/10
D
1/9
D
0/8
HBEN = LOW
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
HBEN = HIGH
DB
11
DB
10
DB
9
DB
8
Low
Low
Low
Low
DB
11
DB
10
DB
9
DB
8
*
D
11
. . . D
0/8
are the ADC data output pins.
DB
11
. . . DB
0
are the 12-bit conversion results. DB
11
is the MSB.
Digital Ground.
Clock Input Pin. An external TTL-compatible clock may be applied to this pin. Alternatively a crystal or
ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18).
Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock is used. See
CLK IN (Pin 17) description for crystal (resonator).
High Byte Enable Input. Its primary function is to multiplex the 12 bits of conversion data onto the lower
D
7
. . . D
0/8
outputs (4 MSBs or 8 LSBs). See pin description 4 . . . 11 and 13 . . . 16. Also disables
conversion start when HBEN is high.
READ Input. This active LOW signal, in conjunction with
CS
, is used to enable the output data three
state drivers and initiates a conversion if CS and HBEN are low.
Chip Select Input. This active LOW signal, in conjunction with
RD
, is used to enable the output data
three-state drivers and initiates a conversion if
RD
and HBEN are low.
BUSY
output indicates converter status.
BUSY
is LOW during conversion.
Negative Supply, –12 V or –15 V.
Positive Supply, +5 V.
1
2
17
DGND
CLK IN
18
CLK OUT
19
HBEN
20
RD
21
CS
22
23
24
BUSY
V
SS
V
DD
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
V
DD
V
SS
BUSY
D
0/8
D
1/9
D
2/10
D
3/11
HBEN
CLK OUT
CLK IN
CS
RD
A
IN
V
REFIN
AGND
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
DGND
ADC912A
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
A
IN
V
REFIN
AGND
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
DGND
C1
+
0V TO 10V
ANALOG INPUT
–
5V
REFERENCE
SOURCE
ADC912A
8-BIT OR 16-BIT P DATA BUS
XTAL = 1MHz, C1 = 0.1 F, C3 = 10 F
C3, C4
= 30pF TO 100pF DEPENDING ON XTAL CHOSEN
24
23
22
21
20
19
18
17
16
15
14
13
+5V
–
12V TO
–
15V
STATUS
OUTPUT
P
CONTROL
INPUTS
C3
XTAL
C4
V
DD
V
SS
D
0/8
D
1/9
D
2/10
D
3/11
HBEN
CLK OUT
CLK IN
BUSY
CS
RD
C2
Figure 10. Basic Connection Diagram
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