參數(shù)資料
型號: ADC71BG
英文描述: 16-Bit ANALOG-TO-DIGITAL CONVERTER
中文描述: 16位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 4/9頁
文件大?。?/td> 96K
代理商: ADC71BG
4
ADC71
Binary (BIN)
Output
INPUT VOLTAGE RANGE AND LSB VALUES
Analog Input
Voltage Range
Defined As:
±
10V
±
5V
±
2.5V
0 to +10V
0 to +5V
0 to +20V
Code
Designation
COB
(1)
or CTC
(2)
COB
(1)
or CTC
(2)
COB
(1)
or CTC
(2)
CSB
(3)
CSB
(3)
CSB
(3)
One Least
Significant
Bit (LSB)
FSR
2
n
n = 12
n = 13
n = 14
20V
2
n
4.88mV
2.44mV
1.22mV
10V
2
n
2.44mV
1.22mV
610
μ
V
5V
2
n
10V
2
n
2.44mV
1.22mV
610
μ
V
5V
2
n
20V
2
n
4.88mV
2.44mV
1.22mV
1.22mV
610
μ
V
305
μ
V
1.22mV
610
μ
V
305
μ
V
Transition Values
MSB
LSB
000 ... 000
(4)
011 ... 111
111 ... 110
+Full Scale
Mid Scale
–Full Scale
+10V–3/2LSB
0
–10V +1/2LSB
+5V–3/2LSB
0
–5V +1/2LSB
+2.5V–3/2LSB
0
–2.5V +1/2LSB
+10V–3/2LSB
+5V
0 +1/2LSB
+5V–3/2LSB
+2.5V
0 +1/2LSB
+20V–3/2LSB
+10V
0 +1/2LSB
NOTES: (1) COB = Complementary Offset Binary. (2) Complementary Two’s Complement—obtained by inverting the most significant bit MSB (pin 1). (3) CSB
= Complementary Straight Binary. (4) Voltages given are the nominal value for transition to the code specified.
FIGURE 2. Timing Relationship of Serial Data to Clock.
FIGURE 3. Timing Relationship of Valid Data to Status.
FIGURE 1. ADC71 Timing Diagram.
NOTES: (1) The convert command must be at least 50ns wide and must remain low during a conversion. The conversion is initiated
by the “trailing edge” of the convert command. (2) 57
μ
s for 16 bits.
Serial
Out
Clock
Out
40-125ns
40-125ns
40-125ns
Bit 16
Status
Bit 16
Valid
“0”
“1”
“1”
“0”
“0”
“1”
“1”
“1”
“0”
“1”
“1”
“0”
“1”
“0”
“0”
“1”
16
“1”
“0”
“0”
“0”
“1”
“1”
“1”
“1”
“1”
“1”
“0”
“0”
“0”
“1”
“1”
“0”
MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Maximum Throughput Time
Conversion Time
(2)
Convert Command
(1)
Internal Clock
Status (EOC)
MBS
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Serial Data Out
LSB
TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions.
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