參數(shù)資料
型號(hào): ADC1443D125HD
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual channel 14-bit ADC; 125 Msps; JESD204B-compliant CGVxpress? serial outputs
封裝: ADC1443D125HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,;
文件頁數(shù): 37/50頁
文件大?。?/td> 408K
代理商: ADC1443D125HD
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
37 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
[1]
Local register
2 to 0
CLK_DIV[1:0]
R/W
clock divider selection
divide by 1
divide by 2
divide by 3
divide by 4
divide by 5
divide by 6
divide by 7
divide by 8
000
001
010
011
100
101
110
111
Table 23.
Default settings are shown highlighted.
Bit
Symbol
CLK_CFG register (address 0007h) bit description
…continued
Access
Value
Description
Table 24.
Default settings are shown highlighted.
Bit
Symbol
7 to 3
-
2 to 0
INTREF[2:0]
[1]
INTERNAL_REF register (address 0008h) bit description
Access
-
R/W
Value
-
-
Description
not used
see
Table 10
Table 25.
Default settings are shown highlighted.
Bit
Symbol
7 to 2
-
1
ADC_B
CHANNEL_SEL register (address 0009h) bit description
Access
-
R/W
Value
-
Description
not used
channel B selection for next SPI operation in local
registers
not selected
selected
channel A selection for next SPI operation in local
registers
not selected
selected
0
1
0
ADC_A
R/W
0
1
Table 26.
Default settings are shown highlighted.
Bit
Symbol
7 to 3
-
2
DATA_SWAP
[1]
OUTPUT_CFG register (address 0011h) bit description
Access
-
R/W
Value
-
Description
not used
output data bits swapped
no swapping
MSBs swapped with LSBs
0
1
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