參數(shù)資料
型號(hào): ADC1413D065HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 14 bits ADC; 65 Msps; serial JESD204A
封裝: ADC1413D065HN/C1<SOT684-7 (HVQFN56)|<<http://www.nxp.com/packages/SOT684-7.html<1<Always Pb-free,;ADC1413D065HN/C1<SOT684-7 (HVQFN56)|<<http://www.nxp.com/packages/SOT684
文件頁數(shù): 36/43頁
文件大?。?/td> 698K
代理商: ADC1413D065HN
ADC1413D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 8 June 2011
36 of 43
NXP Semiconductors
ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
0
LANE_PD
R/W
lane power-down control:
lane is operational
lane is in Power-down mode
0
1
Table 50.
Default values are highlighted.
Bit
Symbol
Lane0_0_Ctrl (address 0870h)
…continued
Access
Value
Description
Table 51.
Default values are highlighted.
Bit
Symbol
7
-
6
SCR_IN_MODE
Lane1_0_Ctrl (address 0871h)
Access
-
R/W
Value
0
Description
not used
defines the input type for scrambler and 8-bit/10-bit units:
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE[1:0]”
(Ser_PRBS_Ctrl register)
defines output type of lane output unit:
normal mode: lane output is the 8-bit/10-bit output unit
constant mode: lane output is set to a constant (0x0)
toggle mode: lane output is toggling between 0x0 and 0x1
PRBS mode: lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
not used
defines lane polarity:
lane polarity is normal
lane polarity is inverted
defines lane clock polarity:
lane clock provided to the serializer is active on positive
edge
lane clock provided to the serializer is active on negative edge
lane power-down control:
lane is operational
lane is in Power-down mode
0
(reset)
1
5 to 4
LANE_MODE[1:0]
R/W
00
(reset)
01
10
11
3
2
-
LANE_POL
-
R/W
0
0
1
1
LANE_CLK_POS_EDGE R/W
0
1
0
LANE_PD
R/W
0
1
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