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參數(shù)資料
| 型號： | ADC1412D105HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 14-bit ADC 105 Msps CMOS or LVDS DDR digital outputs |
| 封裝： | ADC1412D105HN/C1<SOT804-3|<<<1<Always Pb-free,;ADC1412D105HN/C1<SOT804-3|<<<1<Always Pb-free,; |
| 文件頁數(shù)： | 30/43頁 |
| 文件大小： | 1347K |
| 代理商： | ADC1412D105HN |
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ADC1412D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 4 March 2011
30 of 43
NXP Semiconductors
ADC1412D series
Dual 14-bit ADC: CMOS or LVDS DDR digital outputs
Table 17.
[1]
Bit R/W indicates whether it is a read (1) or a write (0) operation.
[2]
Bits W1 and W0 indicate the number of bytes to be transferred (see
Table 18
).
Table 18.
W1
0
0
1
1
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps for a data transfer:
1. A falling edge on pin CS in combination with a rising edge on pin SCLK determine the
start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on pin CS indicates the end of data transmission.
11.6.2
Default modes at start-up
During circuit initialization it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on pin CS triggers a transition to SPI control mode. When the ADC1412D
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see
Figure 33
). Once in SPI control mode, the output data standard
can be changed via bit LVDS_CMOS
(see
Table 24
).
Instruction bytes for the SPI
MSB
7
R/W
[1]
A7
LSB
0
A8
A0
Bit
Description
6
W1
[2]
A6
5
W0
[2]
A5
4
A12
A4
3
A11
A3
2
A10
A2
1
A9
A1
Number of data bytes to be transferred after the instruction bytes
W0
Number of bytes transmitted
0
1 byte
1
2 bytes
0
3 bytes
1
4 bytes or more
Fig 32. SPI mode timing
CS
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D3
D2
D1
D0
D0
D7
D6
D5
D4
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa086
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1412D105HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14bit 72dB 125MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1412D105HN/C1/5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14bit 72dB 125MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1412D105HN-C1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1412D105HN-C18 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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