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  • 參數(shù)資料
    型號(hào): ADC1412D065HN
    廠(chǎng)商: NXP Semiconductors N.V.
    元件分類(lèi): 外設(shè)及接口
    英文描述: Dual 14-bit ADC 65 Msps CMOS or LVDS DDR digital outputs
    封裝: ADC1412D065HN/C1<SOT804-3|<<<1<Always Pb-free,;ADC1412D065HN/C1<SOT804-3|<<<1<Always Pb-free,;
    文件頁(yè)數(shù): 11/43頁(yè)
    文件大?。?/td> 1347K
    代理商: ADC1412D065HN
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    Dynamic characteristics
    [1]
    …continued
    Parameter
    Conditions
    ADC1412D065
    ADC1412D080
    Min
    Typ
    Max
    Min
    Typ
    A
    A
    P
    R
    1
    N
    A
    D
    [1]
    Typical values measured at V
    DDA
    = 3 V, V
    DDO
    = 1.8 V, T
    amb
    = 25
    C; minimum and maximum values are across the full temperature range T
    amb
    =
    40
    C to +85
    C at V
    DDA
    = 3 V,
    V
    DDO
    = 1.8 V; V
    INAP
    V
    INAM
    =
    1 dBFS; V
    INBP
    V
    INBM
    =
    1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
    10.2 Clock and digital output timing
    IMD
    Intermodulation
    distortion
    f
    i
    = 3 MHz
    f
    i
    = 30 MHz
    f
    i
    = 70 MHz
    f
    i
    = 170 MHz
    -
    -
    -
    -
    -
    89
    88
    87
    84
    100
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    89
    88
    87
    85
    100
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    88
    88
    86
    83
    100
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    89
    88
    86
    84
    100
    -
    -
    -
    -
    -
    dBc
    dBc
    dBc
    dBc
    dBc
    ct(ch)
    channel crosstalk f
    i
    = 70 MHz
    Table 7.
    Symbol
    ADC1412D105
    Min
    Typ
    ADC1412D125
    Min
    Typ
    Unit
    Max
    Max
    Max
    Table 8.
    Symbol
    Clock and digital output timing characteristics
    [1]
    Parameter
    Conditions
    ADC1412D065
    Min
    Typ
    ADC1412D080
    Min
    Typ
    ADC1412D105
    Min
    Typ
    ADC1412D125
    Min
    Typ
    Unit
    Max
    Max
    Max
    Max
    Clock timing input: pins CLKP and CLKM
    f
    clk
    clock frequency
    t
    lat(data)
    data latency
    time
    clk
    clock duty cycle DCS_EN = 1
    20
    -
    -
    65
    -
    60
    -
    -
    80
    -
    75
    -
    -
    105
    -
    100
    -
    -
    125
    -
    MHz
    clock
    cycles
    %
    %
    ns
    14
    14
    14
    14
    30
    45
    -
    50
    50
    0.8
    70
    55
    -
    30
    45
    -
    50
    50
    0.8
    70
    55
    -
    30
    45
    -
    50
    50
    0.8
    70
    55
    -
    30
    45
    -
    50
    50
    0.8
    70
    55
    -
    DCS_EN = 0
    t
    d(s)
    sampling delay
    time
    wake-up time
    t
    wake
    CMOS mode timing: pins DA13 to DA0, DB13 to DB0 and DAV
    t
    PD
    propagation
    delay
    DAV
    t
    su
    set-up time
    t
    h
    hold time
    t
    r
    rise time
    DATA
    DAV
    t
    f
    fall time
    DATA
    -
    76
    -
    -
    76
    -
    -
    76
    -
    -
    76
    -
    s
    DATA
    -
    -
    -
    -
    3.9
    4.2
    8.6
    4.8
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    3.9
    4.2
    7.4
    3.4
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    3.9
    4.2
    6.1
    1.8
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    3.9
    4.2
    5.7
    1.4
    -
    -
    -
    -
    -
    -
    -
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    [2]
    0.5
    0.5
    0.5
    2.4
    2.4
    2.4
    0.5
    0.5
    0.5
    2.4
    2.4
    2.4
    0.5
    0.5
    0.5
    2.4
    2.4
    2.4
    0.5
    0.5
    0.5
    2.4
    2.4
    2.4
    [2]
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
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