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| 型號： | ADC1410S125HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Single 14-bit ADC 125 Msps CMOS or LVDS DDR digital outputs |
| 封裝： | ADC1410S125HN/C1<SOT618-1 (HVQFN40)|<<http://www.nxp.com/packages/SOT618-1.html<1<Always Pb-free,;ADC1410S125HN/C1<SOT618-1 (HVQFN40)|<<http://www.nxp.com/packages/SOT618 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 551K |
| 代理商： | ADC1410S125HN |
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ADC1410S_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 24 December 2010
16 of 40
NXP Semiconductors
ADC1410S series
Single 14-bit ADC; CMOS or LVDS DDR digital output
11. Application information
11.1 Device control
The ADC1410S can be controlled via SPI or directly via the I/O pins (Pin control mode).
11.1.1
SPI and PIN control modes
The device enters PIN control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In PIN control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device remains in this mode. The transition from PIN control mode to SPI
control mode is illustrated in
Figure 19
.
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO when a transition is triggered by a falling edge on
CS.
11.1.2
Operating mode selection
The active ADC1410S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see
Table 20
) or by using pins PWD and OE in Pin control mode
(see
Table 10
).
Table 10.
Pin PWD
LOW
LOW
HIGH
HIGH
11.1.3
Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see
Table 23
) or by using pin ODS in Pin control mode. LVDS DDR is selected when
ODS is HIGH, otherwise CMOS is selected.
Fig 19. Control mode selection
R/W
SPI control mode
Pin control mode
Data format
offset binary
Data format
two's complement
LVDS DDR
SDIO/ODS
SCLK/DFS
W1
W0
A12
005aaa039
CMOS
CS
Operating mode selection via pin PWD and OE
Pin OE
LOW
HIGH
LOW
HIGH
Operating mode
Power-up
Power-up
Sleep
Power-down
Output high-Z
no
yes
yes
yes
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| ADC1412D125HN | Dual 14-bit ADC 125 Msps CMOS or LVDS DDR digital outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1410S125HN,551 | 功能描述:模數(shù)轉換器 - ADC SGL 14b ADC 125 MSPS CMOS OR LVDS DDR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1410S125HN/C1,5 | 功能描述:模數(shù)轉換器 - ADC SNGL 14b ADC 125MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1410S125HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Bulk 制造商:Integrated Device Technology Inc 功能描述:IDT ADC1410S125HN-C1 Analog to Digital Converters (ADC) |
| ADC1410S125HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Tape and Reel |
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