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參數(shù)資料
| 型號： | ADC1213S125HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Single 12 bits ADC; 125Msps; serial JESD204A |
| 封裝： | ADC1213S125HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/SOT1152-1.html<1<Always Pb-free,;ADC1213S125HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/S |
| 文件頁數(shù)： | 13/39頁 |
| 文件大小： | 719K |
| 代理商： | ADC1213S125HN |
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ADC1213S_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
13 of 39
NXP Semiconductors
ADC1213S series
Single 12-bit ADC; serial JESD204A interface
11. Application information
11.1 Analog inputs
11.1.1
Input stage description
The analog input of the ADC1213S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
I(cm)
) on pins INP and INM set to 0.5V
DDA
.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
Section 11.2
and
Table 21
).
Figure 6
shows the equivalent circuit of the sample-and-hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.1.2
Anti-kickback circuitry
Anti-kickback circuitry (RC filter in
Figure 7
) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 6.
Input sampling circuit
005aaa185
INP
package
ESD
parasitics
switch
Ron = 15 Ω
Cs
Cs
switch
Ron = 15 Ω
INM
8
7
internal
clock
internal
clock
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| ADC1410S065HN | Single 14-bit ADC 65 Msps CMOS or LVDS DDR digital outputs |
| ADC1410S080HN | Single 14-bit ADC 80 Msps CMOS or LVDS DDR digital outputs |
| ADC1410S105HN | Single 14-bit ADC 105 Msps CMOS or LVDS DDR digital outputs |
| ADC1410S125HN | Single 14-bit ADC 125 Msps CMOS or LVDS DDR digital outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1213S125HN/C1,5 | 功能描述:模數(shù)轉換器 - ADC SGL 12BT ADC 125MSPS SERIAL JESD204A RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1213S125HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Bulk |
| ADC1213S125HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Tape and Reel |
| ADC1215S | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs |
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