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參數(shù)資料
| 型號： | ADC1112D125HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 11-bit ADC; CMOS or LVDS DDR digital outputs |
| 封裝： | ADC1112D125HN/C1<SOT804-3|<<<1<Always Pb-free,;ADC1112D125HN/C1<SOT804-3|<<<1<Always Pb-free,; |
| 文件頁數(shù)： | 24/41頁 |
| 文件大?。?/td> | 565K |
| 代理商： | ADC1112D125HN |
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ADC1112D125
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 March 2011
24 of 41
NXP Semiconductors
ADC1112D125
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
Single-ended or differential clock inputs can be selected via the SPI interface
(see
Table 22
). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via
control bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3
Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see
Table 22
), the circuit can handle signals with duty cycles
of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
11.4.4
Clock input divider
The ADC1112D125 contains an input clock divider that divides the incoming clock by a
factor of 2 (when bit CLKDIV = logic 1; see
Table 22
). This feature allows the user to
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
11.5 Digital outputs
11.5.1
Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to
logic 0 (see
Table 24
).
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in
Figure 29
. The buffer is powered by a separate
AGND/V
DDO
to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core.
Each buffer can be loaded by a maximum of 10 pF.
Fig 29. CMOS digital output buffer
VDDO
ESD
Package
Parasitics
AGND
Dx
005aaa057
50 Ω
LOGIC
DRIVER
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1112D125HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 2IN 125MSPS 66.2dB RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1112D125HN/C1+551 | 制造商:NXP Semiconductors 功能描述:Bulk 制造商:NXP Semiconductors 功能描述:0 |
| ADC1112D125HN-C1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1112D125HN-C18 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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