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參數(shù)資料
| 型號： | ADC1010S065HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Single 10-bit ADC up to 65 Msps, CMOS or LVDS DDR digital outputs |
| 封裝： | ADC1010S065HN/C1<SOT618-1 (HVQFN40)|<<http://www.nxp.com/packages/SOT618-1.html<1<Always Pb-free,;ADC1010S065HN/C1<SOT618-1 (HVQFN40)|<<http://www.nxp.com/packages/SOT618 |
| 文件頁數(shù)： | 24/39頁 |
| 文件大?。?/td> | 296K |
| 代理商： | ADC1010S065HN |
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ADC1010S_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 28 December 2010
24 of 39
NXP Semiconductors
ADC1010S series
Single 10-bit ADC; CMOS or LVDS DDR digital outputs
The output resistance is 50
Ω
and is the combination of an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see
Table 30
):
11.5.2
Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see
Table 23
).
Each output should be terminated externally with a 100
Ω
resistor (typical) at the receiver
side (
Figure 30
) or internally via SPI control bits LVDS_INT_TER[2:0] (see
Figure 31
and
Table 32
).
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATA[1:0]; see
Table 31
) in order to adjust the output logic
voltage levels.
Fig 30. LVDS DDR digital output buffer - externally terminated
Fig 31. LVDS DDR digital output buffer - internally terminated
VDDO
3.5 mA
typ
D
x
P/D
x + 1
P
D
x
M/D
x + 1
M
OGND
100
Ω
005aaa058
+
+
RECEIVER
VDDO
OGND
005aaa059
D
x
P/D
x
+ 1
P
D
x
M/D
x + 1
M
100
Ω
3.5 mA
typ
+
+
RECEIVER
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| ADC1010S065HN | Single 10-bit ADC up to 65 Msps, CMOS or LVDS DDR digital outputs |
| ADC1010S080HN | Single 10-bit ADC up to 80 Msps, CMOS or LVDS DDR digital outputs |
| ADC1010S105HN | Single 10-bit ADC up to 105 Msps, CMOS or LVDS DDR digital outputs |
| ADC1010S125HN | Single 10-bit ADC up to 125 Msps, CMOS or LVDS DDR digital outputs |
| ADC1010S065 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1010S065HN,518 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10bit 62dB 125MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1010S065HN/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs |
| ADC1010S065HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10bit 62dB 125MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1010S065HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Bulk |
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