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參數(shù)資料
| 型號： | ADC001 |
| 元件分類： | ADC |
| 英文描述： | Analog to Digital Converter |
| 中文描述： | 模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 52K |
| 代理商： | ADC001 |
ADC001
Delta Sigma A/D Converter
A third-order, one-bit, Delta-Sigma modulator realized as a 2-1 cascade in the C5 process. The input and reference signals are
implemented differentially. Total input power is about 20mW at 5V. Integrators are correlated double sampled for low offset and
flicker noise. Reset switches are included for incremental ADC operation, in which the integrating capacitors are reset after a
number of samples equal to the Oversampling Ratio (OSR) have been accumulated.
AMI Semiconductor
www.amis.com
14 bits resolution at 70 ksps (OSR=64)
Third order, single bit quantizer architecture in C5 (0.5μ) process
Differential input and reference reduce common mode effects
20mW input power at 5V
External voltage reference and decimation filter required
1.0 Description
Key Performance Features
Value
Voltage supply
Operating current
Voltage reference span (Vref)
Input range
Max clock rate
SINAD
Maximum resolution (at OSR=64)*
5Volts+/-10%
4 mA max
+/- 1V
+/- 65% of Vref
5Mhz
80dB
14 bits
*Requires external decimation filter
2.0 Key Performance Features
3.0 Block Diagram
+
–
SC Integrator
SC Integrator
SC Integrator
Reset
Control
Reset
Reset
Reset
1
1/2
4
1/4
1/2
1
1/2
D
D
D
A
D
∫
∫
∫
Digital Differentiators
+
–
Implemented in decimation filter (not incremental mode)
+Vref
-Vref
+Vref
-Vref
1 bit A/D
1 bit A/D
1 bit D/A
1 bit D/A
–
–
–
–
–
–
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