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參數(shù)資料
| 型號： | ADC-305-3 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LJT 79C 79#22D SKT RECP |
| 中文描述： | 8位，20MHz的的CMOS A / D轉換 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 193K |
| 代理商： | ADC-305-3 |
PIN
FUNCTION
PIN
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
OUTPUT ENABLE (OE)
DGND
BIT 8 (LSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
+DV
S
(+5V)
CLOCK INPUT (A/D CLK)
24
23
22
21
20
19
18
17
16
15
14
13
DGND
REF. BOTTOM (V
RB
)
SELF BIAS 1 (V
RBS
)
AGND
AGND
ANALOG INPUT (V
IN
)
+AV
S
(+5V)
REFERENCE TOP (V
R
T
)
SELF BIAS 2 (V
RTS
)
+AV
S
(+5V)
+AV
S
(+5V)
+DV
S
(+5V)
FEATURES
8-bit resolution, 20MHz min. sampling rate
±LSB max. differential nonlinearity error
18MHz input signal bandwidth
Subranging, S&H enclosed
+5V single power, low 85mW max. dissipation
CMOS compatible logic input
3-State TTL compatible output
Figure 1. Functional Block Diagram
INPUT/OUTPUT CONNECTIONS
ADC-305
8-Bit, 20MHz
CMOS A/D Converters
Both the ADC-305-1 and the ADC-305-3 have the same pin assignment.
GENERAL DESCRIPTION
DATEL's ADC-305 is an 8-bit, 20MHz sampling, CMOS,
subranging (two-pass) A/D converter. It processes signals at
speeds comparable to a full flash converter by using a sub-
ranging conversion technique with multiple comparator blocks,
each containing a sample and hold amplifier.
The ADC-305 features CMOS low power dissipation (60mW
typical) and a wide 18MHz (–1dB) input signal bandwidth.
The ADC-305-1 is packaged in 400 mil 24-pin DIP and the
ADC-305-3 in 300 mil 24-pin SOP.
Other features are CMOS compatible input logic, 3-state TTL
compatible output logic, +5V single power operation, self bias
mode and low cost.
DATEL, Inc., Mansfield, MA 02048-1151 (USA)
Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356
Email: sales@datel.com
Internet www.datel.com
UPPER
ENCODER
(4 BIT)
24 DGND
OUTPUT ENABLE 1
A/D CLK 12
BIT 8 (LSB) 3
BIT 1 (MSB) 10
BIT 7 4
23 V
RB
21 AGND
20 AGND
19 V
IN
15 +AV
S
14 +AV
S
13 +DV
S
18 +AV
S
17 V
RT
22 V
RBS
16 V
RTS
REFERENCE
VOLTAGE
B BLOCK
COMPARATORS
WITH S/H (4 BIT)
UPPER
COMPARATORS
WITH S/H (4 BIT)
LOWER
ENCODER
(4 BIT)
LOWER
ENCODER
(4 BIT)
CLOCK
GENERATOR
UPPER
DATA
LATCHES
LOWER
DATA
LATCHES
A BLOCK
COMPARATORS
WITH S/H (4 BIT)
DGND 2
+DV
S
11
BIT 6 5
BIT 5 6
BIT 4 7
BIT 3 8
BIT 2 9
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