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參數(shù)資料
| 型號： | ADAV803 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | Audio Codec for Recordable DVD |
| 中文描述： | 音頻編解碼器可刻錄DVD |
| 文件頁數(shù)： | 25/56頁 |
| 文件大?。?/td> | 906K |
| 代理商： | ADAV803 |
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ADAV803
Ta
Address
Rev. 0 | Page 25 of 56
ble 10. Profess
ional Audio Standard
Data Bits
7
1
0
6
5
4
3
2
N
Samp
Frequency
Non-
Audio
Pro/
Con
= 1
le
Lock
Emphasis
N + 1
User Bit Management
Alignm
vel
Le
Channel Mode
Use of Auxilia
Sample
N + 2
ry Mode
Bits
ent
Source Word Length
N + 3
el Identification
Chann
N + 4
f
Sc
in
Digital Audio
Reference
Signal
S
al-
g
Sample Frequency (f
S
)
Reserved
N + 5
N + 6
N + 7
N + 8
N + 9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N + 17
N + 18
N + 19
N + 20
N + 21
N + 22
N + 23
N = 0x20 for receiver channel status buffer.
N = 0x38 for transmitter channel status buffer.
Reserved
Alphanumeric Channel Origin Data—First Character
Alphanumeric Channel Origin Data
lphanumeric Channel Origin Data
A
Alphanumeric Channel Origin Data—Last Character
Alphanumeric Channel Destination Data—First Character
ric Channel Destination Data
Alphanume
Alphanumeric Channel Destination Data
Alphanumeric Channel Destination Data—Last Character
Local Sample Address Code—LSW
Local Sample Address Code
Local Sample Address Code
Local Sample Address Code—MSW
Time of Day Code—LSW
Time of Day Code
Time of Day Code
Time of Day Code—MSW
Reliability Flags
Cyclic Redundancy Check Character (CRCC)
Reserved
The standards allow the channel status bits in each subframe to
be independent, but ordinarily the channel status bit in the two
subframes of each frame are the same. The channel status bits
are defined differently for the consumer audio standards and
the professional audio standards. The 192 channel status bits are
organized into 24 bytes and have the interpretations shown in
Table 9 and Table 10.
The SPDIF transmitter and receiver have a comprehensive
register set. The registers give the user full access to the
functions of the SPDIF block, such as detecting nonaudio and
validity bits, Q subcodes, preambles, and so on. The channel
status bits as defined by the IEC60958 and AES3 specifications
are stored in register buffers for ease of use. An autobuffering
function allows channel status bits and user bits read by the
receiver to be copied directly to the transmitter block, removing
the need for user intervention.
Receiver Section
The ADAV803 uses a double-buffering scheme to handle read-
ing channel status and user bit information. The channel status
bits are available as a memory buffer, taking up 24 consecutive
register locations. The user bits are read using an indirect
memory addressing scheme, where the receiver user- bit
indirect-address register is programmed with an offset to the
iver user bit data register can be read
er
read
d
user bit buffer, and the rece
to determine the user bits at that location. Reading the receiv
user bit data register automatically updates the indirect address
register to the next location in the buffer. Typically, the receiver
user bit indirect-address register is programmed to zero (the
start of the buffer), and the receiver user bit data register is
repeatedly until all the buffer’s data has been read. Figure 46 an
Figure 47 show how receiving the channel status bits and user
bits is implemented.
0
SECONDBUFFER
RECEIVE
CS BUFFER
(0x20–0x37)
CHANNEL
STATUS A
(24 × 8 BITS)
DIRIN
CHANNEL
STATUS B
(24 × 8 BITS)
RxCSSWITCH
SPDIF
RECEIVE
BUFFER
FIRST BUFFER
Figure 46. Channel Status Buffer
0
SPDIFIN
0.....7
8.....15
16.....23
FIRST
BUFFER
0.....7
8.....15
16.....23
USER-BIT
BUFFER
ADDRESS = 0x50
ADDRESS = 0x51
RECEIVER USER BIT
INDIRECT ADDRESS
REGISTER
RECEIVER USER BIT
DATA REGISTER
e
37.
are nterrupt/flag bit, RxCSBINT, is provided to
co
ble or
have
e RxCSBINT
ceiver b ffer co
nfiguration register.
u
th
s is av
ormat
inf
of th
re
s
ze o the user b
CON
bit in
own in Table 11.
sh
the
ter, as
Figure 47. Receiver User Bit Buffer
The SPDIF receive buffer is updated continuously by the
incoming SPDIF stream. Once all the channel status bits for th
block (192 for Channel A and 192 for Channel B) are received,
the bits are copied into the receiver channel status buffer. This
buffer stores all 384 bits of channel status information, and the
RxCSSWITCH bit in the channel status switch buffer register
determines whether the Channel A or the Channel B status bits
are required to be read. The receive channel status bit buffer is
24 bytes long and spans the address range from 0x20 to 0x
Because the channel status bits of an SPDIF stream rarely
change, a softw
notify
e host
ntrol that either a new block of channel status
bit
aila
that the first five bytes of channel statu
ion
changed from a previous block. The function
is controlled by the RxBCONF3 bit in t
he
The si
RxB
f
F0
it buffer can be set by programming
the receiver buffer configuration regis
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAV803AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
| ADAV803ASTZ | 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADAV803ASTZ-REEL | 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADAV804AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
| ADAV804ASTZ | 制造商:Analog Devices 功能描述: |
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