參數(shù)資料
型號(hào)： ADAU1701
廠商： Analog Devices, Inc.
英文描述： SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
中文描述： SigmaDSP的28/56-Bit音頻處理器2ADC/4DAC
文件頁(yè)數(shù)： 35/43頁(yè)
文件大?。?/td> 625K
代理商： ADAU1701
Preliminary Technical Data
ADAU1701
Table 47. Serial Input Control Register (2079)
Register Bits
Function
7:5
Unused
4
INPUT_LRCLK polarity
0 = Frame begins on falling edge
1 = Frame begins on rising edge
3
INPUT_BCLK polarity
0 = Data changes on falling edge
1 = Data changes on rising edge
2:0
Serial Input Mode
000 = I
2
S
001 = Left-justified
010 = TDM
011 = Right-justified, 24-bit
100 = Right-justified, 20-bit
101 = Right-justified, 18-bit
110 = Right-justified, 16-bit
SERIAL INPUT CONTROL REGISTER
INPUT_LRCLK Polarity (Bit 4)
When set to 0, the left channel data on the SDATA_INx pins is
clocked when INPUT_LRCLK is low; and the right input data
clocked when INPUT_LRCLK is high. When set to 1, this is
reversed. In TDM mode, when this bit is set to 0, data is clocked
in starting with the next appropriate BCLK edge (set in Bit 3 of
this register) following a falling edge on the INPUT_LRCLK
pin. When set to 1 and running in TDM mode, the input data is
valid on the BCLK edge following a rising edge on the word
clock (INPUT_LRCLK). INPUT_LRCLK can also operate with
a pulse input, rather than a clock. In this case, the first edge of
the pulse is used by the ADAU1701 to start the data frame.
When this polarity bit is set to 0, a low pulse should be used,
and a high pulse should be used when the bit it set to 1.
Rev. PrF | Page 35 of 43
INPUT_BCLK Polarity (Bit 3)
This bit controls on which edge of the bit clock the input data
changes, and on which edge it is clocked. Data changes on the
falling edge of INPUT_BCLK when this bit is set to 0, and on
the rising edge when this bit is set at 1.
Serial Input Mode (Bits 2:0)
These two bits control the data format that the input port
expects to receive. Bits 3 and 4 of this control register will
override the settings in Bits 2:0, so all four bits must be changed
together for proper operation in some modes. The clock
diagrams for these modes are shown in Figure 32, Figure 33,
and Figure 34. Note that for left-justified and right-justified
modes the LRCLK polarity is high, then low, which is opposite
from the default setting of Bit 4.
When these bits are set to accept a TDM input, the ADAU1701’s
data starts after the edge defined by Bit 4. The ADAU1701’s
TDM data stream should be input on pin SDATA_IN0. Figure
35 shows a TDM stream with a high-to-low triggered LRCLK
and data changing on the falling edge of the BCLK. The
ADAU1701 expects the MSB of each data slot delayed by one
BCLK from the beginning of the slot, just like in the stereo I
2
S
format. In TDM mode, Channels 0 to 3 will be in the first half
of the frame, and Channels 4 to 7 will be in the second half.
Figure 36 shows an example of a TDM stream running with a
pulse word clock, which would be used to interface to ADI
codecs in their auxiliary mode. To work in this mode on either
the input or output serial ports, the ADAU1701 should be set to
frame beginning on the rising edge of LRCLK, data changing on
the falling edge of BCLK, and MSB position delayed from the
start of the word clock by one BCLK.
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNEL
LSB
1 /F
S
0
Figure 32. I
2
S Mode—16 to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
1 /F
S
0
Figure 33. Left-Justified Mode—16 to 24 Bits per Channel
相關(guān)PDF資料
PDF描述
ADAU1701JSTZ SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
ADAU1701JSTZ-RL SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADAU1701JSTZ 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類(lèi)型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1701JSTZ-RL 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類(lèi)型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1701MINIBZ 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk
ADAU1702 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs
ADAU1702JSTZ 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類(lèi)型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
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