參數(shù)資料
型號： ADAU1445YSVZ-3A
廠商： Analog Devices Inc
文件頁數(shù)： 18/92頁
文件大?。?/td> 0K
描述： IC SIGMADSP 175MHZ 100TQFP
標準包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應用： 車載音頻
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
ADAU1445/ADAU1446
Rev. A | Page 25 of 92
the idle condition. The R/W bit determines the direction of the
data. A Logic 0 on the LSB of the first byte means that the master
writes information to the peripheral. A Logic 1 on the LSB of
the first byte means that the master reads information from the
peripheral. A data transfer takes place until a stop condition is
encountered. A stop condition occurs when SDA transitions
from low to high while SCL is held high.
shows the
timing of an I2C write.
Burst mode addressing, where the subaddresses are automatically
incremented at word boundaries, can be used for writing large
amounts of data to contiguous memory locations. This increment
happens automatically, unless a stop condition is encountered after
a single-word write. The registers and RAMs in the ADAU1445/
ADAU1446 range in width from one to five bytes; therefore, the
auto-increment feature knows the mapping between subaddresses
and the word length of the destination register (or memory lo-
cation). A data transfer is always terminated by a stop condition.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period, the
user should only issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an in-
valid subaddress is issued by the user, the ADAU1445/ADAU1446
do not issue an acknowledge and return to the idle condition. If
the user exceeds the highest subaddress while in auto-increment
mode, one of two actions is taken. In read mode, the ADAU1445/
ADAU1446 output the highest subaddress register contents
until the master device issues a no acknowledge, indicating the
end of a read. A no-acknowledge condition is where the SDA
line is not pulled low on the ninth clock pulse on SCL. If the
highest subaddress location is reached while in write mode, the
data for the invalid byte is not loaded into any subaddress register, a
no acknowledge is issued by the ADAU1445/ADAU1446, and
the part returns to the idle condition.
I2C Read and Write Operations
Figure 15 shows the sequence of a single-word write operation.
Every ninth clock, the ADAU1445/ADAU1446 issue an
acknowledge by pulling SDA low.
Figure 16 shows the sequence of a burst mode write operation.
This figure shows an example in which the target destination
registers are two bytes. The ADAU1445/ADAU1446 know to
increment the subaddress register every two bytes because the
requested subaddress corresponds to a register or memory area
with a 2-byte word length.
The sequence of a single-word read operation is shown in
Figure 17. Note that, even though this is a read operation, the
first R/W bit is a 0, indicating a write operation. This is because
the subaddress must be written to set up the internal address.
After the ADAU1445/ADAU1446 acknowledge the receipt of
the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W set to 1, indicating
a read operation. This causes the SDA pin of the ADAU1445/
ADAU1446 to switch directions and begin driving data back to
the master. The master then responds every ninth pulse with an
acknowledge pulse to the ADAU1445/ADAU1446.
Figure 18 shows the sequence of a burst mode read operation.
This figure shows an example in which the target read registers
are two bytes. The ADAU1445/ADAU1446 increment the
subaddress every two bytes because the requested subaddress
corresponds to a register or memory area with word lengths of
two bytes. Other address ranges can have a variety of word
lengths, ranging from one to five bytes; the ADAU1445/
ADAU1446 always decode the subaddress and set the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
R/W
0
SCL
SDA
(CONTINUED)
SCL
(CONTINUED)
11
1
ADR
SEL
00
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
DATA BYTE 1
ACK BY
ADAU1445/ADAU1446
ACK BY
ADAU1445/ADAU1446
ACK BY
ADAU1445/ADAU1446
ACK BY
ADAU1445/ADAU1446
STOP BY
MASTER
START BY
MASTER
FRAME 2
SUBADDRESS BYTE 2
07
69
6-
01
3
Figure 13. I2C Write Clocking
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