參數(shù)資料
型號： ADATE206BSV
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： 500 MHz Dual DCL
中文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： MS-026-AED-HD, TQFP-100
文件頁數(shù)： 10/16頁
文件大?。?/td> 246K
代理商： ADATE206BSV
ADATE206
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5, 12, 20, 21, 36,
40, 55, 56, 64, 71,
76, 79, 83, 93, 97,
100
6
7
8
9
10
11
13
14
15
Rev. 0 | Page 10 of 16
Mnemonic
VCOM_1
GNDREF_1
VIOH_1
VIOL_1
GND
Description
Commutation Reference Voltage.
Reference GND for VIOL, VIOH.
Program Voltage for IOH (Sink).
Program Voltage for IOL (Source).
Device Ground.
D_INV_1
VIT_1
VIL_1
VIH_1
CLAMPL_1
CLAMPH_1
CLLM_1
LDEN_1
VTEN_1
Driver Invert.
Driver Term Voltage Reference.
Driver Low Voltage Reference.
Driver High Voltage Reference.
Low Clamp.
High Clamp.
Comparator Low Leakage Mode.
Determines Whether LD Responds to DR_EN_1 or is Disabled (see Table 4).
Low Speed Control Signal. When high, DR_EN_1 forces driver output to VIT. Otherwise, DR_EN_1
forces driver to high impedance (see Table 4).
Negative Power Supply.
16, 17, 33, 43, 59,
60, 84, 87, 92
18 19, 57, 58, 77,
78, 89, 98, 99
22
23
VEE
VCC
Positive Power Supply.
DR_DATA_P_1
DR_DATA_P_T_1
High Speed Data Inputs. Sets high/low state of driver output (see Table 4).
Termination Resistor for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
Complement of DR_DATA_P_1.
High Speed Enable Inputs. Multifunction depending on status of VTEN_1 and LDEN_1. Causes driver
to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit
(see Table 4).
Termination Resistor for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
Termination Resistor for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
Complement of DR_EN_P_1.
No Connect.
High Comparator Output.
Complement of COMP_H_P_1.
Low Comparator Output.
Complement of COMP_L_P_1.
Logic Signals Controlling Driver Slew Rates for Both Drivers. 00 codes for maximum slew voltage; 11
codes for minimum slew voltage.
CMOS Supply (Internal ÷ 2 = Single-Ended Logic Reference).
Complement of COMP_L_P_1.
Low Comparator Output.
Complement of COMP_H_P_1.
High Comparator Output.
24
DR_DATA_N_T_1
25
26
DR_DATA_N_1
DR_EN_P_1
27
DR_EN_P_T_1
28
DR_EN_N_T_1
29
30, 46
31
32
34
35
37, 39
DR_EN_N_1
NC
COMP_H_P_1
COMP_H_N_1
COMP_L_P_1
COMP_L_N_1
SLEW1, SLEW0
38
41
42
44
45
CMOS_VDD
COMP_L_N_2
COMP_L_P_2
COMP_H_N_2
COMP_H_P_2
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