參數(shù)資料
型號(hào): ADATE205
廠商: Analog Devices, Inc.
英文描述: 250 MHz Dual DCL
中文描述: DCL型250 MHz雙
文件頁數(shù): 1/16頁
文件大?。?/td> 247K
代理商: ADATE205
250 MHz Dual DCL
ADATE205
FEATURES
Driver, comparator, and active load
250 MHz toggle rate
Inhibit mode function
Dynamic clamps
Operating voltage range: 1.5 V to +6.5 V
Output voltage swing: 200 mV to 8 V
Four range adjustable slew rate
True/complement data mode bit
100-lead thin quad flat package, exposed pad
Low per channel power
1.15 W with load off
1.50 W with load programmed at 20 mA nominal
Low leakage (<10 nA) in High-Z mode
Driver
50 Ω output resistance
1.6 ns minimum pulse width for a 3 V step
Load: 35 mA to +35 mA maximum current range
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
www.analog.com
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
GENERAL DESCRIPTION
The ADATE205 is a complete, single-chip solution that
performs the pin electronics functions of driver, comparator,
and active load (DCL) for ATE applications. The active load can
be powered down if not used.
The driver is a proprietary design that features three active
modes: data high mode, data low mode, and term mode, as well
as an inhibit state.
The driver has low leakage (<10 nA) in High-Z mode. The
output voltage range is 1.5 V to +6.5 V to accommodate a wide
variety of test devices.
The ADATE205 supports four programmable Tr/Tf times for
applications where slower edge rates are required. The edge rate
selection is done via two static digital CMOS select bits. The
input data to the driver can be inverted using a single CMOS
logic bit. This feature can be used for system calibration or
applications where complement input data is needed.
FUNCTIONAL BLOCK DIAGRAM
DRIVER
(18, 19, 57, 58VCC
1x
COMP_H
IOL
IOH
TEMP
GNDREF
VIOH
VIOL
VCOM
CVL
COMP_L_N
COMP_H_N
COMP_H_P
CVH
LDEN
VTEN
DR_EN_N
DR_EN_N_T
DR_EN_P_T
DR_EN_P
DR_DATA_N
DR_DATA_N_T
DR_DATA_P_T
DR_DATA_P
DR_INV
VIH
VIL
VIT
COMP_L_P
CLLM
DUT
CLAMPH
CLAMPL
T(5 DIODES)
LOGIC
LOAD
7
69
8
68
9
67
6
70
81
95
88
11
66
10
65
22
54
23
53
24
52
25
51
26
50
27
49
28
48
29
47
15
61
14
62
4
72
3
73
2
74
31
45
91
85
32
44
13
63
COMP_L
34
42
35
41
90
86
1
75
(3NC
(8SHIELDS
ADATE205
(16, 17, 33, 43VEE
(5, 12, 20, 21, 36, 40, 55, 5GND
Figure 1.
0
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