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| 型號： | ADA4950-1YCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP DIFF LP 114MA 16LFCSP |
| 標準包裝： | 5,000 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 2900 V/µs |
| -3db帶寬： | 750MHz |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 9.5mA |
| 電流 - 輸出 / 通道： | 114mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 11 V，±1.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 16-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADA4950-1/ADA4950-2
Rev. A | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Rating
Supply Voltage
11 V
Power Dissipation
Input Current, +INx, INx, PD
±5 mA
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
ADA4950-1
40°C to +105°C
ADA4950-2
40°C to +105°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p printed circuit board, as
described in EIA/JESD51-7.
Table 8. Thermal Resistance
Package Type
θJA
θJC
Unit
ADA4950-1, 16-Lead LFCSP (Exposed Pad)
91
28
°C/W
ADA4950-2, 24-Lead LFCSP (Exposed Pad)
65
16
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4950-x package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4950-x. Exceeding a junction temper-
ature of 150°C for an extended period can result in changes in
the silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the quies-
cent power dissipation and the power dissipated in the package
due to the load drive. The quiescent power is the voltage between
the supply pins (VS) times the quiescent current (IS). The power
dissipated due to the load drive depends upon the particular
application. The power dissipated due to the load drive is calcu-
lated by multiplying the load current by the associated voltage
drop across the device. RMS voltages and currents must be used
in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and
power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead
LFCSP (91°C/W) and the dual 24-lead LFCSP (65°C/W) on
a JEDEC standard 4-layer board with the exposed pad soldered
to a PCB pad that is connected to a solid plane.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–40
–20
0
20
40
07957-
004
60
80
100
AMBIENT TEMPERATURE (°C)
MA
XI
MU
M
PO
W
ER
D
ISSI
PA
T
IO
N
(W
)
ADA4950-2
ADA4950-1
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
for a 4-Layer Board
ESD CAUTION
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