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參數(shù)資料
| 型號： | ADA4939-1YCP-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADA4939-1YCP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類型： | 差分 |
| 板類型： | 裸（未填充） |
| 已供物品： | 板 |
| 已用 IC / 零件： | 16-LFCSP 封裝 |
ADA4939-1/ADA4939-2
Rev. 0 | Page 22 of 24
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4939 is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design. This section shows a detailed example of how the
ADA4939-1 was addressed.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4939-1 as possible.
However, the area near the feedback resistors (RF), gain resistors
(RG), and the input summing nodes (Pin 2 and Pin 3) should be
cleared of all ground and power planes (see Figure 51). Clearing
the ground and power planes minimizes any stray capacitance at
these nodes and prevents peaking of the response of the amplifier
at high frequencies.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity four-layer
circuit board, as described in EIA/JESD 51-7.
0
74
29
-0
58
Figure 51. Ground and Power Plane Voiding in Vicinity of RF and RG
The power supply pins should be bypassed as close to the device
as possible and directly to a nearby ground plane. High frequency
ceramic chip capacitors should be used. It is recommended that
two parallel bypass capacitors (1000 pF and 0.1 μF) be used for
each supply. The 1000 pF capacitor should be placed closer to
the device. Further away, low frequency bypassing should be
provided, using 10 μF tantalum capacitors from each supply
to ground.
Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, a symmetrical
layout should be provided to maximize balanced performance.
When routing differential signals over a long distance, PCB
traces should be close together, and any differential wiring
should be twisted such that loop area is minimized. Doing this
reduces radiated energy and makes the circuit less susceptible
to interference.
1.30
0.80
1.30
07
42
9-
0
59
Figure 52. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
0.30
PLATED
VIA HOLE
1.30
GROUND PLANE
POWER PLANE
BOTTOM METAL
TOP METAL
07
42
9-
06
0
Figure 53. Cross-Section of Four-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
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