參數(shù)資料
型號(hào)： ADA4937-2YCPZ-RL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 8/29頁(yè)
文件大小： 0K
描述： IC ADC DRIVER DUAL DIFF 24LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類(lèi)型： ADC 驅(qū)動(dòng)器
應(yīng)用： 數(shù)據(jù)采集
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-VQ（4x4）
包裝： 帶卷 (TR)
Data Sheet
ADA4937-1/ADA4937-2
Rev. D | Page 15 of 28
0
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
1
2
3
4
5
6
7
8
9
10
A
MPL
IT
U
D
E
(V)
TIME (ms)
06591-
043
OUTPUT
POWER-DOWN PULSE
Figure 43. PD Response vs. Time
06591-
044
FREQUENCY (MHz)
CRO
S
T
AL
K
(
d
B)
–140
–120
–130
–110
–100
–90
–80
–70
–40
–50
–60
1
0.3
10
100
1000
INPUT2, OUTPUT1
INPUT1, OUTPUT2
Figure 44. Crosstalk vs. Frequency for ADA4937-2
100
1
10
10M
1M
100k
10k
1k
100
IN
P
U
T
V
OLTA
GE
N
OIS
E
(
nV
/
H
z
)
FREQUENCY (Hz)
06591-
045
Figure 45. Voltage Spectral Noise Density, RTI
10
0.1
1
0.01
1k
100
10
1
0.1
IMPED
A
N
C
E
(
)
FREQUENCY (MHz)
06591-
146
G = 1
Figure 46. Closed-Loop Output Impedance
2
1
–2
1.0
–1.0
–0.5
VIN
0
0.5
0.1
–0.1
–1
0
V
IN
(V)
S
E
TTLIN
G
E
R
OR
(
%
)
TIME (1ns/DIV)
06591-
147
SETTLING ERROR
Figure 47. 0.1% Settling Time
70
–20
50
–300
–250
–200
–150
–100
–50
0
–10
0
10
20
30
40
50
60
1
10G
1G
100M
10M
1M
100k
10k
1k
100
10
OP
E
N
-LOOP
GA
IN
(
dB
)
O
P
E
N-
L
O
P
HAS
E
(
Deg
rees)
FREQUENCY (Hz)
06591-
401
PHASE
GAIN
Figure 48. Open-Loop Gain and Phase vs. Frequency
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